From: Marc Zyngier <maz@kernel.org>
To: Jing Zhang <jingzhangos@google.com>
Cc: KVM <kvm@vger.kernel.org>, KVMARM <kvmarm@lists.linux.dev>,
ARMLinux <linux-arm-kernel@lists.infradead.org>,
Oliver Upton <oupton@google.com>, Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Fuad Tabba <tabba@google.com>, Reiji Watanabe <reijiw@google.com>,
Raghavendra Rao Ananta <rananta@google.com>
Subject: Re: [PATCH v5 0/6] Support writable CPU ID registers from userspace
Date: Mon, 03 Apr 2023 11:30:47 +0100 [thread overview]
Message-ID: <861ql1w948.wl-maz@kernel.org> (raw)
In-Reply-To: <20230402183735.3011540-1-jingzhangos@google.com>
On Sun, 02 Apr 2023 19:37:29 +0100,
Jing Zhang <jingzhangos@google.com> wrote:
>
> This patchset refactors/adds code to support writable per guest CPU ID feature
> registers. Part of the code/ideas are from
> https://lore.kernel.org/all/20220419065544.3616948-1-reijiw@google.com .
> No functional change is intended in this patchset. With the new CPU ID feature
> registers infrastructure, only writtings of ID_AA64PFR0_EL1.[CSV2|CSV3],
> ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon are allowed as KVM does before.
>
> Writable (Configurable) per guest CPU ID feature registers are useful for
> creating/migrating guest on ARM CPUs with different kinds of features.
>
> ---
>
> * v4 -> v5
> - Rebased to 2fad20ae05cb (kvmarm/next)
> Merge branch kvm-arm64/selftest/misc-6,4 into kvmarm-master/next
Please don't do that. Always use a stable, tagged commit, not some
random "commit of the day". If there is a dependency, indicate the
*exact* dependency. Yes, x86 is managed differently.
I'm never going to apply anything on top of an arbitrary commit, so
this makes it difficult for both you and I. I understand that you want
to avoid conflicts, but I really don't mind resolving those.
So please stick to existing tags as a base, and describe the
dependencies you have (in this case, the locking series).
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2023-04-03 10:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-02 18:37 [PATCH v5 0/6] Support writable CPU ID registers from userspace Jing Zhang
2023-04-02 18:37 ` [PATCH v5 1/6] KVM: arm64: Move CPU ID feature registers emulation into a separate file Jing Zhang
2023-04-02 18:37 ` [PATCH v5 2/6] KVM: arm64: Save ID registers' sanitized value per guest Jing Zhang
2023-04-02 18:37 ` [PATCH v5 3/6] KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] Jing Zhang
2023-04-02 18:37 ` [PATCH v5 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer Jing Zhang
2023-04-02 18:37 ` [PATCH v5 5/6] KVM: arm64: Introduce ID register specific descriptor Jing Zhang
2023-04-03 12:27 ` Marc Zyngier
2023-04-03 19:45 ` Jing Zhang
2023-04-02 18:37 ` [PATCH v5 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 Jing Zhang
2023-04-03 14:55 ` Marc Zyngier
2023-04-03 19:50 ` Jing Zhang
2023-04-03 10:30 ` Marc Zyngier [this message]
2023-04-03 19:42 ` [PATCH v5 0/6] Support writable CPU ID registers from userspace Jing Zhang
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