From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37052C3DA42 for ; Wed, 10 Jul 2024 16:05:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0YCq4OreuZ31AmhFjdNdhaxjo5XeXhfuj+C8INWo5lk=; b=fcJJUHvXk5n1wa9AAhMusQbjCq VJWurNlBSH04SMYCGY3qqTEvuL39odQW/c/OIwe23Psc8Bp5uzKq2O4KzVT4P3fwb3zwJgceFE5qy saJIhRcW/4KlBG8OQTPY5c+90VW+eAq7IKOL2lkVrdZ968oNWzQVKUAYKr3oYg5orq7t2cUIpNNXf LJe7GXQKVUC2ijh2GsH4rCCDrezdahVbWQ0DDCmyh/so5KjUffVpttvTOjhb79MxAz59xVMHBm5KQ 87zDoy5WuExW9ocdH6R8V/PF4Et4YSiRZrnqVSKhU4UWoFOh0eNMsr34klMBY91XQFc/c/7ZzEraT Lqu3roig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRZoe-0000000B3z8-05ZF; Wed, 10 Jul 2024 16:05:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRZoN-0000000B3v0-1DqG for linux-arm-kernel@lists.infradead.org; Wed, 10 Jul 2024 16:04:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C43A367; Wed, 10 Jul 2024 09:05:19 -0700 (PDT) Received: from [10.57.8.115] (unknown [10.57.8.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 548B43F762; Wed, 10 Jul 2024 09:04:50 -0700 (PDT) Message-ID: <862c600c-6803-4c25-8234-c8d056e94f23@arm.com> Date: Wed, 10 Jul 2024 17:04:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 08/15] arm64: mm: Avoid TLBI when marking pages as valid To: Will Deacon Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, Catalin Marinas , Marc Zyngier , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni References: <20240701095505.165383-1-steven.price@arm.com> <20240701095505.165383-9-steven.price@arm.com> <20240709115754.GD13242@willie-the-truck> From: Steven Price Content-Language: en-GB In-Reply-To: <20240709115754.GD13242@willie-the-truck> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240710_090455_453946_AF1265A8 X-CRM114-Status: GOOD ( 26.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/07/2024 12:57, Will Deacon wrote: > On Mon, Jul 01, 2024 at 10:54:58AM +0100, Steven Price wrote: >> When __change_memory_common() is purely setting the valid bit on a PTE >> (e.g. via the set_memory_valid() call) there is no need for a TLBI as >> either the entry isn't changing (the valid bit was already set) or the >> entry was invalid and so should not have been cached in the TLB. >> >> Signed-off-by: Steven Price >> --- >> v4: New patch >> --- >> arch/arm64/mm/pageattr.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c >> index 0e270a1c51e6..547a9e0b46c2 100644 >> --- a/arch/arm64/mm/pageattr.c >> +++ b/arch/arm64/mm/pageattr.c >> @@ -60,7 +60,13 @@ static int __change_memory_common(unsigned long start, unsigned long size, >> ret = apply_to_page_range(&init_mm, start, size, change_page_range, >> &data); >> >> - flush_tlb_kernel_range(start, start + size); >> + /* >> + * If the memory is being made valid without changing any other bits >> + * then a TLBI isn't required as a non-valid entry cannot be cached in >> + * the TLB. >> + */ >> + if (pgprot_val(set_mask) != PTE_VALID || pgprot_val(clear_mask)) >> + flush_tlb_kernel_range(start, start + size); >> return ret; > > Can you elaborate on when this actually happens, please? It feels like a > case of "Doctor, it hurts when I do this" rather than something we should > be trying to short-circuit in the low-level code. This is for the benefit of the following patch. When transitioning a page between shared and private we need to change the IPA (to set/clear the top bit). This requires a break-before-make - see __set_memory_enc_dec() in the following patch. The easiest way of implementing the code was to just call __change_memory_common() twice - once to make the entry invalid and then again to make it valid with the new IPA. But that led to a double TLBI which Catalin didn't like[1]. So this patch removes the unnecessary second TLBI by detecting that we're just making the entry valid. Or at least it would if I hadn't screwed up... I should have changed the following patch to ensure that the second call to __change_memory_common was only setting the PTE_VALID bit and not changing anything else (so that the TLBI could be skipped) and forgot to do that. So thanks for making me take a look at this again! Thanks, Steve [1] https://lore.kernel.org/lkml/Zmc3euO2YGh-g9Th@arm.com/