From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56845EB7EC9 for ; Wed, 4 Mar 2026 10:50:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=nWKOg8gvPsLvtbNxnnYGBZukBDSixIlHXpMuxlnxVx8=; b=bMBP3wt/yoyCoMhDW8afZfVkv7 zWHJEwDxT/ku1P/Kbs1VvVimdruZbcxneqLI6S13t1/voMjg/VP+fyYwdgqGOCui8U6k73wK/dwel eQeY3mBiAjF2/VrSUQPzTWPC8PbnnJay0WHnI0eC9fNUMiLuykrjkRh6XyNs0ABn1hG7vSq6YuRMo JvZYEvBxKV4UbTzoDNzM1xYhFpuancWlDUF1CxrBXk0Zh13NjivAOV45+FaWp02bNR7R+2cjGUd2m d8o8+4PDmaUbnz9+yOnD3l/JOpyee27qjqQG7O6YhMTnGt8VXY15aUhqJujljN/eah8OCFl5qKEM/ 96DH3HcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vxjoH-0000000H17I-1uyO; Wed, 04 Mar 2026 10:50:33 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vxjoF-0000000H15p-1ESp for linux-arm-kernel@lists.infradead.org; Wed, 04 Mar 2026 10:50:32 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 8462141A36; Wed, 4 Mar 2026 10:50:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5E371C19423; Wed, 4 Mar 2026 10:50:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772621430; bh=WiCOzsgPlo193jDtqXT2H5mukZhrn1N9GJxmlGUBen8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=iyJtX6s5qWtCR6yK2a+yyDKfwamoTRFTtzx8/U8YZrDVo71tvyzbYAihA51/6bKsr eXDpfAQTbbE9KI0g+swoK/M14moLcJU+nGtJ1OQIVofBYl+bU8PvfWH/sm0afMIDjz rz2ZVIABeeKXPZhwlGYkTcEc4x85SuXAfglQI6NVEo3xpdAfeNrdO42TmOC/lcNIot X/LrNRQSYxZ1Mcv1nTmPpyd1KSgMTD7WMzK2660YYOGhz9kY4P9nrAeqlaNjIXtl6f 62MrKOeI+9h6B/HY3os/uZEfcvDfWyiP4Vz3GR5WHpWKNeu+1cVAeFW2+j9mKTAUop qZIuwdnDgBRPA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vxjoC-0000000G04O-1NAh; Wed, 04 Mar 2026 10:50:28 +0000 Date: Wed, 04 Mar 2026 10:50:27 +0000 Message-ID: <86342f98cs.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v5 17/36] KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask In-Reply-To: <20260226155515.1164292-18-sascha.bischoff@arm.com> References: <20260226155515.1164292-1-sascha.bischoff@arm.com> <20260226155515.1164292-18-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260304_025031_377579_BA4585DF X-CRM114-Status: GOOD ( 42.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 26 Feb 2026 15:59:48 +0000, Sascha Bischoff wrote: > > We only want to expose a subset of the PPIs to a guest. If a PPI does > not have an owner, it is not being actively driven by a device. The > SW_PPI is a special case, as it is likely for userspace to wish to > inject that. > > Therefore, just prior to running the guest for the first time, we need > to finalize the PPIs. A mask is generated which, when combined with > trapping a guest's PPI accesses, allows for the guest's view of the > PPI to be filtered. This mask is global to the VM as all VCPUs PPI > configurations must match. > > In addition, the PPI HMR is calculated. > > Signed-off-by: Sascha Bischoff > Reviewed-by: Jonathan Cameron > --- > arch/arm64/kvm/arm.c | 4 +++ > arch/arm64/kvm/vgic/vgic-v5.c | 46 ++++++++++++++++++++++++++++++ > include/kvm/arm_vgic.h | 9 ++++++ > include/linux/irqchip/arm-gic-v5.h | 17 +++++++++++ > 4 files changed, 76 insertions(+) > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index eb2ca65dc7297..8290c5df0616e 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -935,6 +935,10 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) > return ret; > } > > + ret = vgic_v5_finalize_ppi_state(kvm); > + if (ret) > + return ret; > + > if (is_protected_kvm_enabled()) { > ret = pkvm_create_hyp_vm(kvm); > if (ret) > diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c > index f5cd9decfc26e..db2225aefb130 100644 > --- a/arch/arm64/kvm/vgic/vgic-v5.c > +++ b/arch/arm64/kvm/vgic/vgic-v5.c > @@ -86,6 +86,52 @@ int vgic_v5_probe(const struct gic_kvm_info *info) > return 0; > } > > +int vgic_v5_finalize_ppi_state(struct kvm *kvm) > +{ > + struct kvm_vcpu *vcpu; > + > + if (!vgic_is_v5(kvm)) > + return 0; > + > + /* The PPI state for all VCPUs should be the same. Pick the first. */ > + vcpu = kvm_get_vcpu(kvm, 0); > + > + vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask[0] = 0; > + vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask[1] = 0; > + vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr[0] = 0; > + vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr[1] = 0; vcpu->kvm == kvm. You don't need the indirection (same in most of the function). > + > + for (int i = 0; i < VGIC_V5_NR_PRIVATE_IRQS; i++) { > + int reg = i / 64; > + u64 bit = BIT_ULL(i % 64); > + struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i]; vgic_get_vcpu_irq()? > + > + guard(raw_spinlock_irqsave)(&irq->irq_lock); > + > + /* > + * We only expose PPIs with an owner or the SW_PPI to the > + * guest. > + */ > + if (!irq->owner && > + FIELD_GET(GICV5_HWIRQ_ID, irq->intid) != GICV5_ARCH_PPI_SW_PPI) > + continue; This sort of construct is rather cumbersome, and I see it replicated in quite a few places. How about introducing a couple of basic accessors: #define vgic_v5_get_hwirq_id(x) FIELD_GET(GICV5_HWIRQ_ID, (x)) #define vgic_v5_set_hwirq_id(x) FIELD_PREP(GICV5_HWIRQ_ID, (x)) which is a bit easier on the eye? > + > + /* > + * If the PPI isn't implemented, we can't pass it through to a > + * guest anyhow. > + */ > + if (!(ppi_caps.impl_ppi_mask[reg] & bit)) > + continue; > + > + vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_mask[reg] |= bit; > + > + if (irq->config == VGIC_CONFIG_LEVEL) > + vcpu->kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr[reg] |= bit; > + } > + > + return 0; > +} > + > /* > * Sets/clears the corresponding bit in the ICH_PPI_DVIR register. > */ > diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > index d828861f8298a..a4416afca5efc 100644 > --- a/include/kvm/arm_vgic.h > +++ b/include/kvm/arm_vgic.h > @@ -32,6 +32,8 @@ > #define VGIC_MIN_LPI 8192 > #define KVM_IRQCHIP_NUM_PINS (1020 - 32) > > +#define VGIC_V5_NR_PRIVATE_IRQS 128 > + > #define is_v5_type(t, i) (FIELD_GET(GICV5_HWIRQ_TYPE, (i)) == (t)) > > #define __irq_is_sgi(t, i) \ > @@ -381,6 +383,11 @@ struct vgic_dist { > * else. > */ > struct its_vm its_vm; > + > + /* > + * GICv5 per-VM data. > + */ > + struct gicv5_vm gicv5_vm; Depending how this grows, we may have to move that as part of a union with the previous member (which is obviously v4 specific). > }; > > struct vgic_v2_cpu_if { > @@ -567,6 +574,8 @@ int vgic_v4_load(struct kvm_vcpu *vcpu); > void vgic_v4_commit(struct kvm_vcpu *vcpu); > int vgic_v4_put(struct kvm_vcpu *vcpu); > > +int vgic_v5_finalize_ppi_state(struct kvm *kvm); > + > bool vgic_state_is_nested(struct kvm_vcpu *vcpu); > > /* CPU HP callbacks */ > diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h > index 3e838a3058861..30a1b656daa35 100644 > --- a/include/linux/irqchip/arm-gic-v5.h > +++ b/include/linux/irqchip/arm-gic-v5.h > @@ -380,6 +380,23 @@ struct gicv5_vpe { > bool resident; > }; > > +struct gicv5_vm { > + /* > + * We only expose a subset of PPIs to the guest. This subset > + * is a combination of the PPIs that are actually implemented > + * and what we actually choose to expose. > + */ > + u64 vgic_ppi_mask[2]; > + > + /* > + * The HMR itself is handled by the hardware, but we still need to have > + * a mask that we can use when merging in pending state (only the state > + * of Edge PPIs is merged back in from the guest an the HMR provides a > + * convenient way to do that). > + */ > + u64 vgic_ppi_hmr[2]; > +}; > + > struct gicv5_its_devtab_cfg { > union { > struct { Thanks, M. -- Without deviation from the norm, progress is not possible.