From: Marc Zyngier <maz@kernel.org>
To: Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: linux-arm-kernel@lists.infradead.org,
Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Ryan Roberts <ryan.roberts@arm.com>,
Will Deacon <will@kernel.org>,
Yicong Yang <yangyicong@hisilicon.com>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] arm64: guard AMU register access with ARM64_HAS_AMU_EXTN
Date: Wed, 22 Oct 2025 15:20:16 +0100 [thread overview]
Message-ID: <86347bvx0f.wl-maz@kernel.org> (raw)
In-Reply-To: <20251022133621.178546-1-marek.vasut+renesas@mailbox.org>
On Wed, 22 Oct 2025 14:35:28 +0100,
Marek Vasut <marek.vasut+renesas@mailbox.org> wrote:
>
> The AMU configuration register access may fault and prevent successful
> kernel boot. This can occur for example in case the firmware does not
> allow AMU counter access from EL1. Guard the AMU configuration register
> access with ARM64_HAS_AMU_EXTN to prevent this fault if ARM64_HAS_AMU_EXTN
> Kconfig option is explicitly disabled. Other interaction with the AMU is
> already guarded by similar ifdeffery.
>
> Fixes: 87a1f063464a ("arm64: trap to EL1 accesses to AMU counters from EL0")
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Ryan Roberts <ryan.roberts@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Yicong Yang <yangyicong@hisilicon.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> arch/arm64/mm/proc.S | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 86818511962b6..123538ffeda6b 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -145,7 +145,9 @@ SYM_FUNC_START(cpu_do_resume)
> ubfx x11, x11, #1, #1
> msr oslar_el1, x11
> reset_pmuserenr_el0 x0 // Disable PMU access from EL0
> +alternative_if ARM64_HAS_AMU_EXTN
> reset_amuserenr_el0 x0 // Disable AMU access from EL0
> +alternative_else_nop_endif
Why?
We ensure that the AMU is available in the macro itself by checking
for ID_AA64PFR0_EL1.AMU. If the AMu isn't present on this CPU, we skip
the offending sysreg access. This is similar to what we do for the
PMU.
Does your HW advertise an AMU, but doesn't actually have one?
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-10-22 14:20 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 13:35 [PATCH] arm64: guard AMU register access with ARM64_HAS_AMU_EXTN Marek Vasut
2025-10-22 14:20 ` Marc Zyngier [this message]
2025-10-22 14:33 ` Marek Vasut
2025-10-22 15:02 ` Marc Zyngier
2025-10-22 15:19 ` Catalin Marinas
2025-10-22 15:31 ` Marek Vasut
2025-10-22 15:29 ` Marek Vasut
2025-10-23 14:19 ` Marc Zyngier
2025-10-23 15:58 ` Marek Vasut
2025-10-24 9:27 ` Marc Zyngier
2025-12-30 2:00 ` Marek Vasut
2025-10-23 12:01 ` Yicong Yang
2025-10-23 13:16 ` Marek Vasut
2025-10-23 14:21 ` Marc Zyngier
2025-10-23 14:44 ` Yicong Yang
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