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Mon, 12 Aug 2024 18:58:25 +0100 Date: Mon, 12 Aug 2024 18:58:24 +0100 Message-ID: <8634n91v3z.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Anshuman Khandual , Przemyslaw Gaj Subject: Re: [PATCH v2 13/17] KVM: arm64: nv: Add SW walker for AT S1 emulation In-Reply-To: References: <20240731194030.1991237-1-maz@kernel.org> <20240731194030.1991237-14-maz@kernel.org> <867cco1y4w.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, anshuman.khandual@arm.com, pgaj@cadence.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240812_105831_043762_A42D6046 X-CRM114-Status: GOOD ( 24.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Alex, On Mon, 12 Aug 2024 16:11:02 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On Sat, Aug 10, 2024 at 11:16:15AM +0100, Marc Zyngier wrote: > > Hi Alex, > > > > @@ -136,12 +137,22 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi, > > va = (u64)sign_extend64(va, 55); > > > > /* Let's put the MMU disabled case aside immediately */ > > - if (!(sctlr & SCTLR_ELx_M) || > > - (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)) { > > + switch (wi->regime) { > > + case TR_EL10: > > + if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC) > > + wr->level = S1_MMU_DISABLED; > > In compute_translation_regime(), for AT instructions other than AT S1E2*, when > {E2H,TGE} = {0,1}, regime is Regime_EL10. As far as I can tell, when regime is > Regime_EL10 and TGE is set, stage 1 is disabled, according to > AArch64.S1Enabled() and the decription of the TGE bit. Grmbl... I really dislike E2H=0. May it die a painful death. How about this on top? diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index 10017d990bc3..870e77266f80 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -139,7 +139,19 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi, /* Let's put the MMU disabled case aside immediately */ switch (wi->regime) { case TR_EL10: - if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC) + /* + * If dealing with the EL1&0 translation regime, 3 things + * can disable the S1 translation: + * + * - HCR_EL2.DC = 0 + * - HCR_EL2.{E2H,TGE} = {0,1} + * - SCTLR_EL1.M = 0 + * + * The TGE part is interesting. If we have decided that this + * is EL1&0, then it means that either {E2H,TGE} == {1,0} or + * {0,x}, and we only need to test for TGE == 1. + */ + if (__vcpu_sys_reg(vcpu, HCR_EL2) & (HCR_DC | HCR_TGE)) wr->level = S1_MMU_DISABLED; fallthrough; case TR_EL2: [...] > > switch (desc & GENMASK_ULL(1, 0)) { > case 0b00: > case 0b10: > goto transfault; > case 0b01: > /* Block mapping */ > break; > default: > if (level == 3) > break; > } > > Is this better? Perhaps slightly easier to match against the descriptor layouts, > but I'm not sure it's an improvement over your suggestion. Up to you, no point > in bikeshedding over it. I think I'll leave it as is for now. I'm getting sick of this code... Thanks, M. -- Without deviation from the norm, progress is not possible.