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b=YtmfBZZOTdBbjLSsPW6gSrEQ3L5uE9NhbFjJN9N432vA8co0LnFyjjqtQ00RrFdWU QQQ/5HKs7vyuK5tpPgb2RMWmw4O8NH9JCaEi45g+VXVWZYYPU5Fx6QY+5Juy5cSp1I apHrnwO0opPJ0lHX8tgGiyHxEm66JHjD2y+tzUHe8qxFDSHnDvWSoim2hpleP0H8aV v0Jh1voBexsGkj3PZf8GwoahvaaKUO38HOw/O8eLQ6hXfRcVsH8Xnl3SE3msmtJOXy lMSVPy1BHY1mTnmTUhFmdbrTNyD48lLdRPGEPtE512KR/ZXZyCSzS4G6mdSTOq+jLq QSjEzRcoSOuUg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qJXP3-00CPdq-0R; Wed, 12 Jul 2023 11:49:01 +0100 Date: Wed, 12 Jul 2023 11:49:00 +0100 Message-ID: <86351twgkj.wl-maz@kernel.org> From: Marc Zyngier To: Mostafa Saleh Cc: oliver.upton@linux.dev, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, tabba@google.com, qperret@google.com, will@kernel.org, catalin.marinas@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, james.morse@arm.com, bgardon@google.com, gshan@redhat.com, sudeep.holla@arm.com Subject: Re: [PATCH v2] KVM: arm64: Add missing BTI instructions In-Reply-To: <20230706152240.685684-1-smostafa@google.com> References: <20230706152240.685684-1-smostafa@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: smostafa@google.com, oliver.upton@linux.dev, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, tabba@google.com, qperret@google.com, will@kernel.org, catalin.marinas@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, james.morse@arm.com, bgardon@google.com, gshan@redhat.com, sudeep.holla@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230712_034904_562465_CBBF1700 X-CRM114-Status: GOOD ( 23.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 06 Jul 2023 16:22:40 +0100, Mostafa Saleh wrote: > > Some bti instructions were missing from > commit b53d4a272349 ("KVM: arm64: Use BTI for nvhe") > > 1) kvm_host_psci_cpu_entry > kvm_host_psci_cpu_entry is called from __kvm_hyp_init_cpu through "br" > instruction as __kvm_hyp_init_cpu resides in idmap section while > kvm_host_psci_cpu_entry is in hyp .text so the offset is larger than > 128MB range covered by "b". > Which means that this function should start with "bti j" instruction. > > LLVM which is the only compiler supporting BTI for Linux, adds "bti j" > for jump tables or by when taking the address of the block [1]. > Same behaviour is observed with GCC. > > As kvm_host_psci_cpu_entry is a C function, this must be done in > assembly. > > Another solution is to use X16/X17 with "br", as according to ARM > ARM DDI0487I.a RLJHCL/IGMGRS, PACIASP has an implicit branch > target identification instruction that is compatible with > PSTATE.BTYPE 0b01 which includes "br X16/X17" > And the kvm_host_psci_cpu_entry has PACIASP as it is an external > function. > Although, using explicit "bti" makes it more clear than relying on > which register is used. > > A third solution is to clear SCTLR_EL2.BT, which would make PACIASP > compatible PSTATE.BTYPE 0b11 ("br" to other registers). > However this deviates from the kernel behaviour (in bti_enable()). > > 2) Spectre vector table > "br" instructions are generated at runtime for the vector table > (__bp_harden_hyp_vecs). > These branches would land on vectors in __kvm_hyp_vector at offset 8. > As all the macros are defined with valid_vect/invalid_vect, it is > sufficient to add "bti j" at the correct offset. > > [1] https://reviews.llvm.org/D52867 > > Fixes: b53d4a272349 ("KVM: arm64: Use BTI for nvhe") > Signed-off-by: Mostafa Saleh > Reported-by: Sudeep Holla > --- > v1 -> v2: > - Add another missing bti in spectre vector table. > v1: https://lore.kernel.org/all/20230705171632.3912123-1-smostafa@google.com/ Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel