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Tue, 16 May 2023 17:01:38 +0100 Date: Tue, 16 May 2023 17:01:37 +0100 Message-ID: <86353wmfj2.wl-maz@kernel.org> From: Marc Zyngier To: Cornelia Huck Cc: Shameerali Kolothum Thodi , Jing Zhang , KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta Subject: Re: [PATCH v8 0/6] Support writable CPU ID registers from userspace In-Reply-To: <87a5y4gy0b.fsf@redhat.com> References: <20230503171618.2020461-1-jingzhangos@google.com> <2ef9208dabe44f5db445a1061a0d5918@huawei.com> <868rdomtfo.wl-maz@kernel.org> <1a96a72e87684e2fb3f8c77e32516d04@huawei.com> <87cz30h4nx.fsf@redhat.com> <867ct8mnel.wl-maz@kernel.org> <87a5y4gy0b.fsf@redhat.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: cohuck@redhat.com, shameerali.kolothum.thodi@huawei.com, jingzhangos@google.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oupton@google.com, will@kernel.org, pbonzini@redhat.com, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, tabba@google.com, reijiw@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230516_090141_572431_8E5242C5 X-CRM114-Status: GOOD ( 33.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 16 May 2023 15:19:00 +0100, Cornelia Huck wrote: > > On Tue, May 16 2023, Marc Zyngier wrote: > > > On Tue, 16 May 2023 12:55:14 +0100, > > Cornelia Huck wrote: > >> > >> Do you have more concrete ideas for QEMU CPU models already? Asking > >> because I wanted to talk about this at KVM Forum, so collecting what > >> others would like to do seems like a good idea :) > > > > I'm not being asked, but I'll share my thoughts anyway! ;-) > > > > I don't think CPU models are necessarily the most important thing. > > Specially when you look at the diversity of the ecosystem (and even > > the same CPU can be configured in different ways at integration > > time). Case in point, Neoverse N1 which can have its I/D caches made > > coherent or not. And the guest really wants to know which one it is > > (you can only lie in one direction). > > > > But being able to control the feature set exposed to the guest from > > userspace is a huge benefit in terms of migration. > > Certainly; the important part is that we can keep the guest ABI > stable... which parts match to a "CPU model" in the way other > architectures use it is an interesting question. It almost certainly > will look different from e.g. s390, where we only have to deal with a > single manufacturer. > > I'm wondering whether we'll end up building frankenmonster CPUs. We already do. KVM hides a bunch of things we don't want the guest to see, either because we don't support the feature, or that we want to present it with a different shape (cache topology, for example), and these combination don't really exist in any physical implementation. Which is why I don't really buy the "CPU model" concept as defined by x86 and s390. We already are in a vastly different place. The way I see it, you get a bunch of architectural features that can be enabled/disabled depending on the underlying HW, hypervisor's capabilities and userspace input. On top of that, there is a layer of paint that tells you what is the overall implementation you could be running on (that's what MIDR+REVIDR+AIDR tell you) so that you can apply some unspeakable, uarch-specific hacks that keep the machine going (got to love these CPU errata). > Another interesting aspect is how KVM ends up influencing what the guest > sees on the CPU level, as in the case where we migrate across matching > CPUs, but with a different software level. I think we want userspace to > control that to some extent, but I'm not sure if this fully matches the > CPU model context. I'm not sure I get the "different software level" part. Do you mean VMM revisions? Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel