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Fri, 24 Feb 2023 10:54:52 +0000 Date: Fri, 24 Feb 2023 10:54:52 +0000 Message-ID: <86356vxrib.wl-maz@kernel.org> From: Marc Zyngier To: Colton Lewis Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, ricarkol@google.com, sveith@amazon.de, dwmw2@infradead.org Subject: Re: [PATCH 07/16] KVM: arm64: timers: Allow physical offset without CNTPOFF_EL2 In-Reply-To: References: <20230216142123.2638675-8-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: coltonlewis@google.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, ricarkol@google.com, sveith@amazon.de, dwmw2@infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230224_025459_151344_5FF13068 X-CRM114-Status: GOOD ( 37.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 23 Feb 2023 22:40:25 +0000, Colton Lewis wrote: > > > Marc Zyngier writes: > > > +/* If _pred is true, set bit in _set, otherwise set it in _clr */ > > +#define assign_clear_set_bit(_pred, _bit, _clr, _set) \ > > + do { \ > > + if (_pred) \ > > + (_set) |= (_bit); \ > > + else \ > > + (_clr) |= (_bit); \ > > + } while (0) > > + > > I don't think the do-while wrapper is necessary. Is there any reason > besides style guide conformance? It is if you want to avoid a stray ';'. > > + /* > > + * We have two possibility to deal with a physical offset: > > + * > > + * - Either we have CNTPOFF (yay!) or the offset is 0: > > + * we let the guest freely access the HW > > + * > > + * - or neither of these condition apply: > > + * we trap accesses to the HW, but still use it > > + * after correcting the physical offset > > + */ > > + if (!has_cntpoff() && timer_get_offset(map->direct_ptimer)) > > + tpt = tpc = true; > > If there are only two possibilites, then two different booleans makes > things more complicated than it has to be. Each boolean denotes a different architectural state. They are separate so that someone can: - easily understand what is going on - affect one without affecting the other when extending this code The "common state" is what we had before, and it was a real pig to reverse engineer *my own code*. Yes, this is job security, but I don't think that's a good enough reason! ;-) So I contend that two bools make things far simpler to reason about these things. > > > + assign_clear_set_bit(tpt, CNTHCTL_EL1PCEN << 10, set, clr); > > + assign_clear_set_bit(tpc, CNTHCTL_EL1PCTEN << 10, set, clr); > > Might be good to name the 10 something like VHE_SHIFT so people know why > it is applied. VHE_SHIFT really doesn't mean more that '10' because it doesn't tell you *why* you have to do this. The real way of solving that one is it move everything to the sysreg generation *and* have a way to contextualise the sysreg generation based on features and other controls (see the discussion about FEAT_CCIDX as an example). > > > + > > + > > + timer_set_traps(vcpu, &map); > > } > > > bool kvm_timer_should_notify_user(struct kvm_vcpu *vcpu) > > @@ -1293,27 +1363,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) > > } > > > /* > > - * On VHE system, we only need to configure the EL2 timer trap > > register once, > > - * not for every world switch. > > - * The host kernel runs at EL2 with HCR_EL2.TGE == 1, > > - * and this makes those bits have no effect for the host kernel > > execution. > > + * If we have CNTPOFF, permanently set ECV to enable it. > > */ > > void kvm_timer_init_vhe(void) > > { > > - /* When HCR_EL2.E2H ==1, EL1PCEN and EL1PCTEN are shifted by 10 */ > > - u32 cnthctl_shift = 10; > > - u64 val; > > - > > - /* > > - * VHE systems allow the guest direct access to the EL1 physical > > - * timer/counter. > > - */ > > - val = read_sysreg(cnthctl_el2); > > - val |= (CNTHCTL_EL1PCEN << cnthctl_shift); > > - val |= (CNTHCTL_EL1PCTEN << cnthctl_shift); > > if (cpus_have_final_cap(ARM64_HAS_ECV_CNTPOFF)) > > - val |= CNTHCTL_ECV; > > - write_sysreg(val, cnthctl_el2); > > + sysreg_clear_set(cntkctl_el1, 0, CNTHCTL_ECV); > > } > > What is the reason for moving these register writes from initialization > to vcpu load time? This contradicts the comment that says this is only > needed once and not at every world switch. Seems like doing more work > for no reason. You did notice that the comment got *removed*, so that there is no contradiction? You also understand that with a physical offset, and in the absence of CNTPOFF, we cannot grant access to the physical counter/timer to the guest? Finally, given that we always have to write various bits of CNTKCTL_EL1 for other reasons, moving this settings shouldn't result in any extra work (specially considering that they don't require any extra synchronisation). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel