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Sat, 10 Oct 2026 11:10:31 +0000 Date: Sat, 10 Oct 2026 12:10:30 +0100 Message-ID: <864iet3j6h.wl-maz@kernel.org> From: Marc Zyngier To: Myria Sarvay Cc: Michael Reeves , Oliver Upton , Catalin Marinas , Will Deacon , Mark Rutland , Yureka Lilian , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Sven Peter , Janne Grunau , Neal Gompa , asahi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4 In-Reply-To: References: <20261008-apple-m3-m4-kvm-v1-0-7bb4cbf3d63b@gmail.com> <20261008-apple-m3-m4-kvm-v1-2-7bb4cbf3d63b@gmail.com> <86cxtk2utm.wl-maz@kernel.org> <86bj932ssc.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: myrialsarvay@gmail.com, michael.reeves077@gmail.com, oupton@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, yureka@cyberchaos.dev, fuad.tabba@linux.dev, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, sven@kernel.org, j@jannau.net, neal@gompa.dev, asahi@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 10 Oct 2026 11:54:16 +0100, Myria Sarvay wrote: > > Hi Marc, > > (Resending because I forgot to reply all, sorry Marc) > > On Fri, Oct 09, 2026 at 09:16:03AM +0100, Marc Zyngier wrote: > > On Fri, 09 Oct 2026 01:03:57 +0100, > > Michael Reeves wrote: > > > > > > > I can provide the binary (and a few scripts) to test this easily. > > > > Should they have been fixed, we can always create a second > > > > implementation list to cover the PMU. > > > > > > Can you please send that so we can try? That would be much > > > appreciated, thank you. > > > > I've sent you (and Yureka) details over IRC. If you need help with > > setting things up, let me know directly. > > > > Thanks, > > > > M. > > > > -- > > Without deviation from the norm, progress is not possible. > > I've tested the patches on my M3 Max (t6031-j514c), and without these > patches, it SErrors, and with them (and including the M3/M4 MIDRs in > the has_vgic_v3 list in arch/arm64/kernel/cpufeature.c) it doesn't > SError, and the iso boots correctly to a login getty. Thanks for letting me know. When you post v2 to fix the has_vgic_v3 list, please collect the details of what this was tested on in the cover letter, it may become useful in the future. Cheers, M. -- Without deviation from the norm, progress is not possible.