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From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Jonathan Corbet <corbet@lwn.net>,
	Oliver Upton <oliver.upton@linux.dev>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [RFC 5/8] KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED
Date: Tue, 16 Apr 2024 09:15:54 +0100	[thread overview]
Message-ID: <864jc1soxx.wl-maz@kernel.org> (raw)
In-Reply-To: <58cdb927-a2d9-4af4-900f-2132472afe9f@arm.com>

On Tue, 16 Apr 2024 06:46:13 +0100,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> On 4/12/24 16:35, Marc Zyngier wrote:
> > kvm_init_nv_sysregs() to ensure that these new registers have the
> > correct RES0/RES1 behaviour depending on the supported feature set for
> > the guest.
> 
> Following might be sufficient for MDSELR_EL1, but wondering if these fine
> grained control registers (HDFG[RW]TR2_EL2) need to be completely defined
> for the entire guest feature set, probably required.

Yes, you should check for all features defining a valid bit in these
registers, and apply the correct mask if the feature isn't advertised
to the guest, even if KVM doesn't currently support the feature at
all. This is a bit cumbersome at first, but we don't have to revisit
it when the feature gets enabled, which is a massive maintainability
improvement.

It also means that we just have to read the documentation and match it
against the code, which should be pretty trivial.

> 
>        /* HDFG[RW]TR2_EL2 */
>        res0 = res1 = 0;
>        if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9))
>                res0 |= HDFGRTR2_EL2_nMDSELR_EL1;
>        set_sysreg_masks(kvm, HDFGRTR2_EL2, res0 | HDFGRTR2_EL2_RES0, res1);
>        set_sysreg_masks(kvm, HDFGWTR2_EL2, res0 | HDFGWTR2_EL2_RES0, res1);

Yup, this looks sensible for that particular bit. A few more to
go... ;-)

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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  reply	other threads:[~2024-04-16  8:16 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-05  8:00 [RFC 0/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Anshuman Khandual
2024-04-05  8:00 ` [RFC 1/8] arm64/sysreg: Add register fields for MDSELR_EL1 Anshuman Khandual
2024-04-05 12:52   ` Mark Brown
2024-04-05  8:00 ` [RFC 2/8] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Anshuman Khandual
2024-04-05 12:59   ` Mark Brown
2024-04-05  8:00 ` [RFC 3/8] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Anshuman Khandual
2024-04-05 13:08   ` Mark Brown
2024-04-05  8:00 ` [RFC 4/8] arm64/sysreg: Update ID_AA64MMFR0_EL1 register Anshuman Khandual
2024-04-05 13:16   ` Mark Brown
2024-04-05  8:00 ` [RFC 5/8] KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED Anshuman Khandual
2024-04-05 10:15   ` Marc Zyngier
2024-04-12  2:41     ` Anshuman Khandual
2024-04-12 11:05       ` Marc Zyngier
2024-04-16  5:46         ` Anshuman Khandual
2024-04-16  8:15           ` Marc Zyngier [this message]
2024-04-05  8:00 ` [RFC 6/8] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Anshuman Khandual
2024-04-05  8:00 ` [RFC 7/8] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Anshuman Khandual
2024-04-05  8:00 ` [RFC 8/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Anshuman Khandual
2024-04-05 10:26   ` Marc Zyngier
2024-04-16  3:13     ` Anshuman Khandual
2024-04-16  3:54 ` [RFC 0/8] " Anshuman Khandual

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