From: Marc Zyngier <maz@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Peter Maydell <peter.maydell@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Aishwarya.TCV@arm.com
Subject: Re: [PATCH v2 3/3] KVM: arm64: Limit clearing of ID_{AA64PFR0,PFR1}_EL1.GIC to userspace irqchip
Date: Mon, 10 Nov 2025 13:11:05 +0000 [thread overview]
Message-ID: <865xbiuj6e.wl-maz@kernel.org> (raw)
In-Reply-To: <aRHf6x5umkTYhYJ3@finisterre.sirena.org.uk>
On Mon, 10 Nov 2025 12:51:55 +0000,
Mark Brown <broonie@kernel.org> wrote:
>
> On Thu, Oct 30, 2025 at 12:27:07PM +0000, Marc Zyngier wrote:
> > Now that the idreg's GIC field is in sync with the irqchip, limit
> > the runtime clearing of these fields to the pathological case where
> > we do not have an in-kernel GIC.
> >
> > While we're at it, use the existing API instead of open-coded
> > accessors to access the ID regs.
>
> Today's next/pending-fixes is showing regressions on a range of physical
> arm64 platforms (including at least a bunch of A53 systems, an A55 one
> and an A72 one) in the steal_time selftest which bisect to this patch.
> We get asserts in the kernel on ID register sets:
>
> [ 150.872407] WARNING: CPU: 0 PID: 2865 at arch/arm64/kvm/sys_regs.c:2353 kvm_set_vm_id_reg+0x9c/0xf4
>
> ...
>
> [ 151.045312] Call trace:
> [ 151.047780] kvm_set_vm_id_reg+0x9c/0xf4 (P)
> [ 151.052098] kvm_finalize_sys_regs+0x88/0x240
> [ 151.056504] kvm_arch_vcpu_run_pid_change+0xb4/0x438
> [ 151.061527] kvm_vcpu_ioctl+0x92c/0x9d0
Please name the platforms this fails on. Here, on a sample of one A72
box, I don't see the issue:
maz@sy-borg:~$ ./steal_time
Random seed: 0x6b8b4567
TAP version 13
1..4
ok 1 vcpu0
ok 2 vcpu1
ok 3 vcpu2
ok 4 vcpu3
# Totals: pass:4 fail:0 xfail:0 xpass:0 skip:0 error:0
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-11-10 13:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-30 12:27 [PATCH v2 0/3] KVM: arm64: Fix handling of ID_PFR1_EL1.GIC Marc Zyngier
2025-10-30 12:27 ` [PATCH v2 1/3] KVM: arm64: Make all 32bit ID registers fully writable Marc Zyngier
2025-10-30 12:27 ` [PATCH v2 2/3] KVM: arm64: Set ID_{AA64PFR0,PFR1}_EL1.GIC when GICv3 is configured Marc Zyngier
2025-10-30 12:27 ` [PATCH v2 3/3] KVM: arm64: Limit clearing of ID_{AA64PFR0,PFR1}_EL1.GIC to userspace irqchip Marc Zyngier
2025-11-10 12:51 ` Mark Brown
2025-11-10 13:11 ` Marc Zyngier [this message]
2025-11-10 14:15 ` Mark Brown
2025-11-10 14:29 ` Marc Zyngier
2025-11-10 17:20 ` Mark Brown
2025-11-07 1:34 ` [PATCH v2 0/3] KVM: arm64: Fix handling of ID_PFR1_EL1.GIC Oliver Upton
2025-11-07 10:06 ` Suzuki K Poulose
2025-11-08 11:24 ` Marc Zyngier
2025-11-08 11:58 ` Marc Zyngier
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