From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBF11CCA476 for ; Mon, 6 Oct 2025 15:55:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lpyqZrPl+Z0QLpDFjeR+Sx0txUodqBQiZUQNeSFTO2o=; b=1jGKjE/tlgJHGLvg9q3+nmbjP1 UgiMlZz+6iaZb1FYymvU2sBMa2F4Q1ddfGvnpqQOrxcLIVpAcd/akJF36FNmzaI++nh4fw2kP8iEp OkKuKOV7n3Up13YBYdUkPss5JnVDILINAz6uFXSHh0wkIAPkPwJZlfJJv/GN4lbhiOl5gbHFFi/6A /e3J2J5omYKs/TFWne06TPPDYO3pOr3m72P90DRNeAgSU03XVVrPglelU+H+tjJtMmyGs9Gs0VMz9 hMGlfQeGYmm7VESn5+cS3If+ldQPfXMp/36eawSEB/KZxKQoB5RDsyaXIRubEU/31ge4CciBDRSLo z0hanLdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v5nZ2-00000000KKj-0dul; Mon, 06 Oct 2025 15:55:52 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v5nZ0-00000000KKb-3M0h for linux-arm-kernel@lists.infradead.org; Mon, 06 Oct 2025 15:55:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 3E8D960581; Mon, 6 Oct 2025 15:55:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF5F2C4CEF5; Mon, 6 Oct 2025 15:55:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759766149; bh=PNewJkNL6CSZlcvcVRzdF4vG0QntxYg8acRL1wWz8xQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=llB2pjvrsfAQsrqHn6tONxtl59AYRr+QlQq0ELqOELOEZyntMxjcpFMmkvl4KBGSB 7dvb5gB33pbJd9n3W7WBc12p+LFft9mgaeN9cz5ue6V6v2mZhiKxMRQNPDnFVZznCd I2mPvizxGNY/GOabl2Aq7QrrBeaqQdFkkcrsogpLWyFxg1ynh9AlJdO/Akalb08deV 8gHGQf1MoH00M/m6l0xJ5ruejk27SCdDvq2GZRScYVk3C2JvKYQvdeTOfsaagkSVgl oZQvtjHABSDDctU2eG7cNU/i3mCxW3PbfdEiw2qGs0yECldiVnjAK1otZscPZKHcvj /Vd5kyZJKVisg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v5nYx-0000000BtEa-23VH; Mon, 06 Oct 2025 15:55:47 +0000 Date: Mon, 06 Oct 2025 16:55:47 +0100 Message-ID: <865xcsyqgs.wl-maz@kernel.org> From: Marc Zyngier To: Ulf Hansson Cc: "Rafael J . Wysocki" , Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Maulik Shah , Sudeep Holla , Daniel Lezcano , Vincent Guittot , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] arm64: smp: Implement cpus_has_pending_ipi() In-Reply-To: <20251003150251.520624-3-ulf.hansson@linaro.org> References: <20251003150251.520624-1-ulf.hansson@linaro.org> <20251003150251.520624-3-ulf.hansson@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ulf.hansson@linaro.org, rafael@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@linutronix.de, quic_mkshah@quicinc.com, sudeep.holla@arm.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 03 Oct 2025 16:02:44 +0100, Ulf Hansson wrote: > > To add support for keeping track of whether there may be a pending IPI > scheduled for a CPU or a group of CPUs, let's implement > cpus_has_pending_ipi() for arm64. > > Note, the implementation is intentionally lightweight and doesn't use any > additional lock. This is good enough for cpuidle based decisions. > > Signed-off-by: Ulf Hansson > --- > arch/arm64/kernel/smp.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c > index 68cea3a4a35c..dd1acfa91d44 100644 > --- a/arch/arm64/kernel/smp.c > +++ b/arch/arm64/kernel/smp.c > @@ -55,6 +55,8 @@ > > #include > > +static DEFINE_PER_CPU(bool, pending_ipi); > + > /* > * as from 2.5, kernels no longer have an init_tasks structure > * so we need some other way of telling a new secondary core > @@ -1012,6 +1014,8 @@ static void do_handle_IPI(int ipinr) > > if ((unsigned)ipinr < NR_IPI) > trace_ipi_exit(ipi_types[ipinr]); > + > + per_cpu(pending_ipi, cpu) = false; > } > > static irqreturn_t ipi_handler(int irq, void *data) > @@ -1024,10 +1028,26 @@ static irqreturn_t ipi_handler(int irq, void *data) > > static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) > { > + unsigned int cpu; > + > + for_each_cpu(cpu, target) > + per_cpu(pending_ipi, cpu) = true; > + Why isn't all of this part of the core IRQ management? We already track things like timers, I assume for similar reasons. If IPIs have to be singled out, I'd rather this is done in common code, and not on a per architecture basis. > trace_ipi_raise(target, ipi_types[ipinr]); > arm64_send_ipi(target, ipinr); > } > > +bool cpus_has_pending_ipi(const struct cpumask *mask) > +{ > + unsigned int cpu; > + > + for_each_cpu(cpu, mask) { > + if (per_cpu(pending_ipi, cpu)) > + return true; > + } > + return false; > +} > + The lack of memory barriers makes me wonder how reliable this is. Maybe this is relying on the IPIs themselves acting as such, but that's extremely racy no matter how you look at it. M. -- Without deviation from the norm, progress is not possible.