Re: [BUG][PATCH v8 4/6] arm64: Make _midr_in_range_list() an exported function

[Marc Zyngier <maz@kernel.org>]

On Tue, 15 Apr 2025 11:57:50 +0100,
Ada Couprie Diaz <ada.coupriediaz@arm.com> wrote:
> 
> Hello,
> 
> I discovered that this patch breaks boot for some CPUs when building
> the default defconfig plus KASAN. This is still the case in v6.15-rc1
> and rc2.
> 
> This patch marks `is_midr_in_range_list` as position independent but
> it isn't, breaking early boot when instrumented with KASAN and
> `CONFIG_RANDOMIZE_BASE` enabled.
> 
> The breaking usage seems to be in `kaslr_requires_kpti()` called in
> `early_map_kernel()`.
> My testing on an AMD Seattle board does crash, but newer machines
> implementing E0PD do not crash as they do not need to check MIDRs in
> `kaslr_requires_kpti()`.
> `is_mdr_in_range_list` did work in PI code previously because it was
> `inline`, which this patch changes.

OK, this is much more of a pain than I thought.

I tried bringing the various helpers into the PI section, but it ended
up being extremely ugly.

More importantly, this is something that is pretty much at odds with
the whole idea of the MIDR override -- it happens way earlier than we
can populate the table.

The thing is, the only reason we need to do this is that we need to
support the Cavium SEFAC (Sorry Excuse For A Computer) that cannot run
with KPTI.

I can restore harmony with the following hack. But maybe we should
just prune TX from the kernel and be done with this contraption.

	M.

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index d1cc0571798bf..bdfefca166baa 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -292,6 +292,20 @@ static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
 	return _model == model && rv >= rv_min && rv <= rv_max;
 }
 
+static inline bool __is_midr_in_range(struct midr_range const *range)
+{
+	return midr_is_cpu_model_range(read_cpuid_id(), range->model,
+				       range->rv_min, range->rv_max);
+}
+
+static inline bool __is_midr_in_range_list(struct midr_range const *ranges)
+{
+	while (ranges->model)
+		if (__is_midr_in_range(ranges++))
+			return true;
+	return false;
+}
+
 struct target_impl_cpu {
 	u64 midr;
 	u64 revidr;
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index 30a29e88994ba..e54a384826dc1 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -72,6 +72,17 @@ extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
 extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot);
 extern void mark_linear_text_alias_ro(void);
 
+static inline bool cpu_has_e0pd(void)
+{
+	if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
+		u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
+		return (cpuid_feature_extract_unsigned_field(mmfr2,
+							     ID_AA64MMFR2_EL1_E0PD_SHIFT));
+	}
+
+	return false;
+}
+
 /*
  * This check is triggered during the early boot before the cpufeature
  * is initialised. Checking the status on the local CPU allows the boot
@@ -87,12 +98,8 @@ static inline bool kaslr_requires_kpti(void)
 	 * E0PD does a similar job to KPTI so can be used instead
 	 * where available.
 	 */
-	if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
-		u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
-		if (cpuid_feature_extract_unsigned_field(mmfr2,
-						ID_AA64MMFR2_EL1_E0PD_SHIFT))
-			return false;
-	}
+	if (cpu_has_e0pd())
+		return false;
 
 	/*
 	 * Systems affected by Cavium erratum 24756 are incompatible
@@ -108,5 +115,21 @@ static inline bool kaslr_requires_kpti(void)
 	return true;
 }
 
+/* Same as the above, but limited to the local CPU, ignoring the MIDR list */
+static inline bool __kaslr_requires_kpti(void)
+{
+	if (cpu_has_e0pd())
+		return false;
+
+	if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
+		extern const struct midr_range cavium_erratum_27456_cpus[];
+
+		if (__is_midr_in_range_list(cavium_erratum_27456_cpus))
+			return false;
+	}
+
+	return true;
+}
+
 #endif	/* !__ASSEMBLY__ */
 #endif
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index b55f5f7057502..ba8e05d640c7e 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -32,8 +32,7 @@ static inline bool is_midr_in_range(struct midr_range const *range)
 	int i;
 
 	if (!target_impl_cpu_num)
-		return midr_is_cpu_model_range(read_cpuid_id(), range->model,
-					       range->rv_min, range->rv_max);
+		return __is_midr_in_range(range);
 
 	for (i = 0; i < target_impl_cpu_num; i++) {
 		if (midr_is_cpu_model_range(target_impl_cpus[i].midr,
diff --git a/arch/arm64/kernel/pi/map_kernel.c b/arch/arm64/kernel/pi/map_kernel.c
index e57b043f324b5..2df76d44a1072 100644
--- a/arch/arm64/kernel/pi/map_kernel.c
+++ b/arch/arm64/kernel/pi/map_kernel.c
@@ -245,7 +245,7 @@ asmlinkage void __init early_map_kernel(u64 boot_status, void *fdt)
 	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) {
 		u64 kaslr_seed = kaslr_early_init(fdt, chosen);
 
-		if (kaslr_seed && kaslr_requires_kpti())
+		if (kaslr_seed && __kaslr_requires_kpti())
 			arm64_use_ng_mappings = true;
 
 		kaslr_offset |= kaslr_seed & ~(MIN_KIMG_ALIGN - 1);

-- 
Without deviation from the norm, progress is not possible.