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Thu, 14 Nov 2024 12:20:00 +0000 Date: Thu, 14 Nov 2024 12:20:00 +0000 Message-ID: <865xoqvwgf.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, Mark Rutland , stable@vger.kernel.org Subject: Re: [PATCH] arm64: tls: Fix context-switching of tpidrro_el0 when kpti is enabled In-Reply-To: <20241114095332.23391-1-will@kernel.org> References: <20241114095332.23391-1-will@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_042005_001851_AD296C33 X-CRM114-Status: GOOD ( 23.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 14 Nov 2024 09:53:32 +0000, Will Deacon wrote: > > Commit 18011eac28c7 ("arm64: tls: Avoid unconditional zeroing of > tpidrro_el0 for native tasks") tried to optimise the context switching > of tpidrro_el0 by eliding the clearing of the register when switching > to a native task with kpti enabled, on the erroneous assumption that > the kpti trampoline entry code would already have taken care of the > write. > > Although the kpti trampoline does zero the register on entry from a > native task, the check in tls_thread_switch() is on the *next* task and > so we can end up leaving a stale, non-zero value in the register if the > previous task was 32-bit. > > Drop the broken optimisation and zero tpidrro_el0 unconditionally when > switching to a native 64-bit task. > > Cc: Mark Rutland > Cc: > Fixes: 18011eac28c7 ("arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks") > Signed-off-by: Will Deacon > --- > > You fix one side-channel and introduce another... :( > > arch/arm64/kernel/process.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index 3e7c8c8195c3..2bbcbb11d844 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -442,7 +442,7 @@ static void tls_thread_switch(struct task_struct *next) > > if (is_compat_thread(task_thread_info(next))) > write_sysreg(next->thread.uw.tp_value, tpidrro_el0); > - else if (!arm64_kernel_unmapped_at_el0()) > + else > write_sysreg(0, tpidrro_el0); > > write_sysreg(*task_user_tls(next), tpidr_el0); Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.