From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFED2C43381 for ; Fri, 15 Feb 2019 10:35:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9CD6B21924 for ; Fri, 15 Feb 2019 10:35:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="YadS5FJH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9CD6B21924 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tZrvVX2aSHyAZGaF5CIdTsanae0jqB9IqNpZwDw89Bk=; b=YadS5FJHcqdtud E/jszCr14O4dOJ4XrMbObVdqbiebLqdBXMtZ6TqISzRkrmT+ZwhEOnH8+qBLtkNjPCqZ1/HBzzQAz lGvoklqcqCjwD0KJMbCh5h0aZEBD2H0AMUjXJSNVY8Bt1nCud5IWWPsb+NsF0KE5ApyaxVMU326QH 71Ezw1bnvHWCTEBrRLI9yhT0268PfrhFhRM8BauuhKQ6AHl//RWVfBQs4rqPFXsEOQPh4ri5ozAwW xuwdqAPT89+TvsXJdxKbNgDI3DkqDy20VUj7hD7Z+HHjUzvqO8Nv8BBJrp3/lLUwdt0auriC7FFZr bz1+o6UBUfxRMgP+25+w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guaq0-0007l3-Jg; Fri, 15 Feb 2019 10:35:20 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guapx-0007kC-56 for linux-arm-kernel@lists.infradead.org; Fri, 15 Feb 2019 10:35:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A318EBD; Fri, 15 Feb 2019 02:35:16 -0800 (PST) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51D2E3F557; Fri, 15 Feb 2019 02:35:05 -0800 (PST) Date: Fri, 15 Feb 2019 10:34:54 +0000 Message-ID: <865ztls5kh.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Ard Biesheuvel Subject: Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table In-Reply-To: References: <20190213132738.10294-1-ard.biesheuvel@linaro.org> <20190213132738.10294-2-ard.biesheuvel@linaro.org> <325ae70b-6520-a186-c65f-8ab29a5be3a5@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190215_023517_203306_8476F3F0 X-CRM114-Status: GOOD ( 29.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-efi , Catalin Marinas , Will Deacon , Linux-MM , James Morse , Andrew Morton , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 14 Feb 2019 16:55:28 +0000, Ard Biesheuvel wrote: > > On Thu, 14 Feb 2019 at 16:48, Marc Zyngier wrote: > > > > Hi Ard, > > > > On 13/02/2019 13:27, Ard Biesheuvel wrote: > > > In the irqchip and EFI code, we have what basically amounts to a quirk > > > to work around a peculiarity in the GICv3 architecture, which permits > > > the system memory address of LPI tables to be programmable only once > > > after a CPU reset. This means kexec kernels must use the same memory > > > as the first kernel, and thus ensure that this memory has not been > > > given out for other purposes by the time the ITS init code runs, which > > > is not very early for secondary CPUs. > > > > > > On systems with many CPUs, these reservations could overflow the > > > memblock reservation table, and this was addressed in commit > > > eff896288872 ("efi/arm: Defer persistent reservations until after > > > paging_init()"). However, this turns out to have made things worse, > > > since the allocation of page tables and heap space for the resized > > > memblock reservation table itself may overwrite the regions we are > > > attempting to reserve, which may cause all kinds of corruption, > > > also considering that the ITS will still be poking bits into that > > > memory in response to incoming MSIs. > > > > > > So instead, let's grow the static memblock reservation table on such > > > systems so it can accommodate these reservations at an earlier time. > > > This will permit us to revert the above commit in a subsequent patch. > > > > > > Signed-off-by: Ard Biesheuvel > > > --- > > > arch/arm64/include/asm/memory.h | 11 +++++++++++ > > > include/linux/memblock.h | 3 --- > > > mm/memblock.c | 10 ++++++++-- > > > 3 files changed, 19 insertions(+), 5 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > > > index e1ec947e7c0c..7e2b13cdd970 100644 > > > --- a/arch/arm64/include/asm/memory.h > > > +++ b/arch/arm64/include/asm/memory.h > > > @@ -332,6 +332,17 @@ static inline void *phys_to_virt(phys_addr_t x) > > > #define virt_addr_valid(kaddr) \ > > > (_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr)) > > > > > > +/* > > > + * Given that the GIC architecture permits ITS implementations that can only be > > > + * configured with a LPI table address once, GICv3 systems with many CPUs may > > > + * end up reserving a lot of different regions after a kexec for their LPI > > > + * tables, as we are forced to reuse the same memory after kexec (and thus > > > + * reserve it persistently with EFI beforehand) > > > + */ > > > +#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS) > > > +#define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + 2 * NR_CPUS) > > > > Since GICv3 has 1 pending table per CPU, plus one global property table, > > can we make this 2 * NR_CPUS + 1? Or is that enough already? > > > > Ah, I misread the code then. That would mean we'll only need 1 extra > slot per CPU. > > So I will change this to > > > > +#define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + NR_CPUS) > > considering that INIT_MEMBLOCK_REGIONS defaults to 128, so that one > global table is already accounted for. Look good to me. Thanks, M. -- Jazz is not dead, it just smell funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel