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Tue, 31 Mar 2026 17:18:24 +0000 Date: Tue, 31 Mar 2026 18:18:24 +0100 Message-ID: <867bqr534v.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Joey Gouly , "yuzenghui@huawei.com" , Suzuki Poulose , "oupton@kernel.org" , "broonie@kernel.org" , nd Subject: Re: [PATCH 09/15] KVM: arm64: vgic-v5: align priority comparison with other GICs In-Reply-To: <729851f0e7d277d308adf04d0008156a01f482bb.camel@arm.com> References: <20260326153530.3981879-1-maz@kernel.org> <20260326153530.3981879-10-maz@kernel.org> <729851f0e7d277d308adf04d0008156a01f482bb.camel@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joey.Gouly@arm.com, yuzenghui@huawei.com, Suzuki.Poulose@arm.com, oupton@kernel.org, broonie@kernel.org, nd@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 31 Mar 2026 16:09:10 +0100, Sascha Bischoff wrote: >=20 > On Thu, 2026-03-26 at 15:35 +0000, Marc Zyngier wrote: > > The way the effective priority mask is computed, and then compared > > to the priority of an interrupt to decide whether to wake-up or not, > > is slightly odd, and breaks at the limits. > >=20 > > This could result in spurious wake-ups that are undesirable. > >=20 > > Adopt the GICv[23] logic instead, which checks that the priority > > value > > is strictly lower than the mask. > >=20 > > Fixes: 933e5288fa971 ("KVM: arm64: gic-v5: Check for pending PPIs") > > Link: > > https://sashiko.dev/#/patchset/20260319154937.3619520-1-sascha.bischoff= %40arm.com > > Signed-off-by: Marc Zyngier > > --- > > =C2=A0arch/arm64/kvm/vgic/vgic-v5.c | 4 ++-- > > =C2=A01 file changed, 2 insertions(+), 2 deletions(-) > >=20 > > diff --git a/arch/arm64/kvm/vgic/vgic-v5.c > > b/arch/arm64/kvm/vgic/vgic-v5.c > > index 0f269321ece4b..75372bbfb6a6a 100644 > > --- a/arch/arm64/kvm/vgic/vgic-v5.c > > +++ b/arch/arm64/kvm/vgic/vgic-v5.c > > @@ -238,7 +238,7 @@ static u32 > > vgic_v5_get_effective_priority_mask(struct kvm_vcpu *vcpu) > > =C2=A0 */ > > =C2=A0 priority_mask =3D FIELD_GET(FEAT_GCIE_ICH_VMCR_EL2_VPMR, > > cpu_if->vgic_vmcr); > > =C2=A0 > > - return min(highest_ap, priority_mask + 1); > > + return min(highest_ap, priority_mask); >=20 > Hi Marc, >=20 > This part of your change (dropping the `- 1`) is not correct for GICv5. > The GICv[23] PMR works differently to the GICv5 PCR. >=20 > For GICv[23] the mask is exclusive, i.e., only higher priority (lower > numerical value) interrupts are of sufficient priority to be signalled. >=20 > For GICv5, the priority of an interrupt can be equal to or higher than > (numerically lower than) the mask. See DMSQKF in the GICv5 spec: >=20 > A physical interrupt has Sufficient priority to be signaled when all of > the following are true: > * The priority of the interrupt is higher than the physical running > priority for the Physical Interrupt Domain. > * The priority of the interrupt is equal to or higher than the > Physical Priority Mask for the Physical Interrupt Domain. > =20 > Therefore, we require this `+ 1` for the priority_mask in order to allow > us to combine the active priority and priority mask. Else, they operate on > different scales. >=20 > I'd tried to explain this in a comment that lies just outside the diff, > but hadn't explicitly called out that GICv5 operates differently to > GICv[23] in this regard. Apologies. Nothing to apologise about, this is me not being able to read. > =20 > > =C2=A0} > > =C2=A0 > > =C2=A0/* > > @@ -367,7 +367,7 @@ bool vgic_v5_has_pending_ppi(struct kvm_vcpu > > *vcpu) > > =C2=A0 > > =C2=A0 scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) > > =C2=A0 has_pending =3D (irq->enabled && > > irq_is_pending(irq) && > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 irq->priority <=3D > > priority_mask); > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 irq->priority < > > priority_mask); >=20 > I agree that this was wrong and should never have included the > equality. This was definitely a bug! Cool. I'll revert the revert of the first hunk and keep the second one. Thanks! M. --=20 Without deviation from the norm, progress is not possible.