From: Marc Zyngier <maz@kernel.org>
To: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
Yang Guo <guoyang2@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Subject: Re: [PATCH] clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value
Date: Mon, 26 Sep 2022 08:46:51 -0400 [thread overview]
Message-ID: <867d1q8fr8.wl-maz@kernel.org> (raw)
In-Reply-To: <20220926113003.13121-1-zhangshaokun@hisilicon.com>
On Mon, 26 Sep 2022 07:30:03 -0400,
Shaokun Zhang <zhangshaokun@hisilicon.com> wrote:
Please Cc the clocksource maintainers (now added) so that they know
what is going on.
>
> From: Yang Guo <guoyang2@huawei.com>
>
> CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
> so fix them according to the Arm ARM as follows:
Please quote the location of the information: DDi 0487I.a, Table I2-4
"CNTBaseN memory map"
>
> Offset Register Type Description
> 0x000 CNTPCT[31:0] RO Physical Count register.
> 0x004 CNTPCT[63:32] RO
> 0x008 CNTVCT[31:0] RO Virtual Count register.
> 0x00C CNTVCT[63:32] RO
>
> Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
Cc: stable@vger.kernel.org
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Yang Guo <guoyang2@huawei.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
With the above:
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2022-09-26 12:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 11:30 [PATCH] clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value Shaokun Zhang
2022-09-26 12:46 ` Marc Zyngier [this message]
2022-09-26 13:12 ` Shaokun Zhang
2022-09-26 13:17 ` Marc Zyngier
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