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From: Marc Zyngier <maz@kernel.org>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
	"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
	Joey Gouly <Joey.Gouly@arm.com>,
	Suzuki Poulose <Suzuki.Poulose@arm.com>,
	"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	Timothy Hayes <Timothy.Hayes@arm.com>,
	"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>
Subject: Re: [PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support
Date: Thu, 19 Mar 2026 18:26:17 +0000	[thread overview]
Message-ID: <868qbn65h2.wl-maz@kernel.org> (raw)
In-Reply-To: <20260319154937.3619520-1-sascha.bischoff@arm.com>

On Thu, 19 Mar 2026 15:49:42 +0000,
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
> 
> This is v7 of the patch series to add the virtual GICv5 [1] device
> (vgic_v5). Only PPIs are supported by this initial series, and the
> vgic_v5 implementation is restricted to the CPU interface,
> only. Further patch series are to follow in due course, and will add
> support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS.

[...]

I have queued this, but it didn't go as planned. QEMU guests end-up
with a NULL pointer dereference, because we are now setting ops pretty
early in the game, while QEMU creates an irqchip very late.

The obvious solution is what you originally had in your v6, which is
to set the ops in kvm_timer_enable(), but to do it over *all* the
timer interrupts in order not to break NV is a fairly subtle way(we
still want to use the .get_input_level() callback on all timers.

I ended up with the following diff, which I folded in the respective
patches, meaning that patch 4 can be dropped altogether.

Thanks,

	M.

diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
index f6d2f0246d057..67b989671b410 100644
--- a/arch/arm64/kvm/arch_timer.c
+++ b/arch/arm64/kvm/arch_timer.c
@@ -1106,8 +1106,6 @@ static void timer_context_init(struct kvm_vcpu *vcpu, int timerid)
 void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
 {
 	struct arch_timer_cpu *timer = vcpu_timer(vcpu);
-	struct timer_map map;
-	struct irq_ops *ops;
 
 	for (int i = 0; i < NR_KVM_TIMERS; i++)
 		timer_context_init(vcpu, i);
@@ -1121,15 +1119,6 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
 
 	hrtimer_setup(&timer->bg_timer, kvm_bg_timer_expire, CLOCK_MONOTONIC,
 		      HRTIMER_MODE_ABS_HARD);
-
-	get_timer_map(vcpu, &map);
-
-	ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 :
-				      &arch_timer_irq_ops;
-
-	kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_vtimer), ops);
-	if (map.direct_ptimer)
-		kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_ptimer), ops);
 }
 
 /*
@@ -1600,6 +1589,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
 {
 	struct arch_timer_cpu *timer = vcpu_timer(vcpu);
 	struct timer_map map;
+	struct irq_ops *ops;
 	int ret;
 
 	if (timer->enabled)
@@ -1620,6 +1610,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
 
 	get_timer_map(vcpu, &map);
 
+	ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 :
+				      &arch_timer_irq_ops;
+
+	for (int i = 0; i < nr_timers(vcpu); i++)
+		kvm_vgic_set_irq_ops(vcpu, timer_irq(vcpu_get_timer(vcpu, i)), ops);
+
 	ret = kvm_vgic_map_phys_irq(vcpu,
 				    map.direct_vtimer->host_timer_irq,
 				    timer_irq(map.direct_vtimer));
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index e7d07752143be..36410f7cd2ad3 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -526,6 +526,15 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 
 	vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO;
 
+	/* Set up the timer */
+	kvm_timer_vcpu_init(vcpu);
+
+	kvm_pmu_vcpu_init(vcpu);
+
+	kvm_arm_pvtime_vcpu_init(&vcpu->arch);
+
+	vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu;
+
 	/*
 	 * This vCPU may have been created after mpidr_data was initialized.
 	 * Throw out the pre-computed mappings if that is the case which forces
@@ -537,15 +546,6 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 	if (err)
 		return err;
 
-	/* Set up the timer */
-	kvm_timer_vcpu_init(vcpu);
-
-	kvm_pmu_vcpu_init(vcpu);
-
-	kvm_arm_pvtime_vcpu_init(&vcpu->arch);
-
-	vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu;
-
 	err = kvm_share_hyp(vcpu, vcpu + 1);
 	if (err)
 		kvm_vgic_vcpu_destroy(vcpu);

-- 
Without deviation from the norm, progress is not possible.


  parent reply	other threads:[~2026-03-19 18:26 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-19 15:49 [PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support Sascha Bischoff
2026-03-19 15:49 ` [PATCH v7 01/41] KVM: arm64: vgic-v3: Drop userspace write sanitization for ID_AA64PFR0.GIC on GICv5 Sascha Bischoff
2026-03-19 15:50 ` [PATCH v7 02/41] KVM: arm64: vgic: Rework vgic_is_v3() and add vgic_host_has_gicvX() Sascha Bischoff
2026-03-19 15:50 ` [PATCH v7 03/41] KVM: arm64: Return early from kvm_finalize_sys_regs() if guest has run Sascha Bischoff
2026-03-19 15:50 ` [PATCH v7 04/41] KVM: arm64: Init vcpu prior to the timers and PMU Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 05/41] KVM: arm64: vgic: Split out mapping IRQs and setting irq_ops Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 06/41] arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 07/41] arm64/sysreg: Add GICR CDNMIA encoding Sascha Bischoff
2026-03-19 15:51 ` [PATCH v7 08/41] KVM: arm64: gic-v5: Add ARM_VGIC_V5 device to KVM headers Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 09/41] KVM: arm64: gic: Introduce interrupt type helpers Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 10/41] KVM: arm64: gic-v5: Add Arm copyright header Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 11/41] KVM: arm64: gic-v5: Detect implemented PPIs on boot Sascha Bischoff
2026-03-19 15:52 ` [PATCH v7 12/41] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE Sascha Bischoff
2026-03-23 13:37   ` Mark Brown
2026-03-23 13:50     ` Marc Zyngier
2026-03-23 14:08       ` Mark Brown
2026-03-23 17:59         ` Marc Zyngier
2026-03-24 12:47   ` Mark Brown
2026-03-24 14:48     ` Marc Zyngier
2026-03-24 14:53       ` Mark Brown
2026-03-24 15:25         ` Marc Zyngier
2026-03-24 18:16           ` Mark Brown
2026-03-19 15:53 ` [PATCH v7 13/41] KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs Sascha Bischoff
2026-03-19 15:53 ` [PATCH v7 14/41] KVM: arm64: gic-v5: Add emulation for ICC_IAFFIDR_EL1 accesses Sascha Bischoff
2026-03-19 15:53 ` [PATCH v7 15/41] KVM: arm64: gic-v5: Trap and emulate ICC_IDR0_EL1 accesses Sascha Bischoff
2026-03-19 15:53 ` [PATCH v7 16/41] KVM: arm64: gic-v5: Add vgic-v5 save/restore hyp interface Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 17/41] KVM: arm64: gic-v5: Implement GICv5 load/put and save/restore Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 18/41] KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 19/41] KVM: arm64: gic: Introduce queue_irq_unlock to irq_ops Sascha Bischoff
2026-03-19 15:54 ` [PATCH v7 20/41] KVM: arm64: gic-v5: Implement PPI interrupt injection Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 21/41] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 22/41] KVM: arm64: gic-v5: Clear TWI if single task running Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 23/41] KVM: arm64: gic-v5: Check for pending PPIs Sascha Bischoff
2026-03-19 15:55 ` [PATCH v7 24/41] KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 25/41] KVM: arm64: Introduce set_direct_injection irq_op Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 26/41] KVM: arm64: gic-v5: Implement direct injection of PPIs Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 27/41] KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE Sascha Bischoff
2026-03-19 15:56 ` [PATCH v7 28/41] KVM: arm64: gic-v5: Create and initialise vgic_v5 Sascha Bischoff
2026-03-19 15:57 ` [PATCH v7 29/41] KVM: arm64: gic-v5: Initialise ID and priority bits when resetting vcpu Sascha Bischoff
2026-03-19 15:57 ` [PATCH v7 30/41] irqchip/gic-v5: Introduce minimal irq_set_type() for PPIs Sascha Bischoff
2026-03-19 15:57 ` [PATCH v7 31/41] KVM: arm64: gic-v5: Enlighten arch timer for GICv5 Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 32/41] KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 33/41] KVM: arm64: gic: Hide GICv5 for protected guests Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 34/41] KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests Sascha Bischoff
2026-03-19 15:58 ` [PATCH v7 35/41] KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 36/41] KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 37/41] KVM: arm64: gic-v5: Probe for GICv5 device Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 38/41] Documentation: KVM: Introduce documentation for VGICv5 Sascha Bischoff
2026-03-19 15:59 ` [PATCH v7 39/41] KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI Sascha Bischoff
2026-03-19 16:00 ` [PATCH v7 40/41] KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest Sascha Bischoff
2026-03-19 16:00 ` [PATCH v7 41/41] KVM: arm64: selftests: Add no-vgic-v5 selftest Sascha Bischoff
2026-03-19 18:26 ` Marc Zyngier [this message]
2026-03-19 18:50 ` (subset) [PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support Marc Zyngier

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