From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABE6F109190B for ; Thu, 19 Mar 2026 18:26:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Eakklbn74VCv4Bufa58WLRD+OmPRfbKrfKbhGMGnOpM=; b=hQ2boZ14dQ/uw6W/nbOq6yYyRu ragfzdP6ujNYFL1kcMM7RQbPgDg/SrLsi3nuZ6v9lMZqFn8bHljG4yUJW3G5rDPxNidD60+hQi1fH WqrOZwxDJiSfGVp+NDFpvROCXR808Y3dFI8VLv8SEjVlI/OOy72vnPC4jzYxQzcu8m5c6G3gO0BJ9 MB/jgLOGwcKDoEmSFIDMAxejzTngqvXyy8jKlWoF39niSc03DNPonbY1+uzIJZLaqyfNxYYR/nWCV tb6tz7DlxvQxtgFTLWpaocpMEgJTYS3o0LXzhlOtaEcDZkI9WhUZZpaoF6gWxK6kIV8waCg4U9/Qh YRfkrtcA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w3I4d-0000000BLAy-0b8S; Thu, 19 Mar 2026 18:26:23 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w3I4b-0000000BL9y-0U4X for linux-arm-kernel@lists.infradead.org; Thu, 19 Mar 2026 18:26:21 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 7E9FF60053; Thu, 19 Mar 2026 18:26:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EB2DC19424; Thu, 19 Mar 2026 18:26:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773944780; bh=GBQQbLO2a4zuF3uSSSHniBNg4oXiGd3KKh0MkAh+ZLI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=f+90WUPOSqYqST8rwA0x76yqe7boMwbsDN7P3SAgdK6wvuKz8G0R/nS/vx9mCEVMJ HQ+5KfrAjjtBHBGgV7hCS3OFBJJyO2GrcZAff70lc/01Y44GHeFgR/95eqcCbBh32f MFQsQ7/EZstr0l8AWY2uiJ3c/7vBQFejqBGzlrb4sWpQcv5j6O0yAeokdQsq97XRFc TFcTHEn/2tzeABskVo5j1INGQ8p9GcRaIeGsD36BT/QBZul/xN3U/QrqWIDj69Ja+r uipBwdbAoOMBkapNIQYCpH6jWi6HFuqh1lwChiXfGN307VF7cBw2EB+2NcIT6lZigh KsKTZWy6XthNA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w3I4X-00000003lWw-3Nvm; Thu, 19 Mar 2026 18:26:17 +0000 Date: Thu, 19 Mar 2026 18:26:17 +0000 Message-ID: <868qbn65h2.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support In-Reply-To: <20260319154937.3619520-1-sascha.bischoff@arm.com> References: <20260319154937.3619520-1-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 19 Mar 2026 15:49:42 +0000, Sascha Bischoff wrote: > > This is v7 of the patch series to add the virtual GICv5 [1] device > (vgic_v5). Only PPIs are supported by this initial series, and the > vgic_v5 implementation is restricted to the CPU interface, > only. Further patch series are to follow in due course, and will add > support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS. [...] I have queued this, but it didn't go as planned. QEMU guests end-up with a NULL pointer dereference, because we are now setting ops pretty early in the game, while QEMU creates an irqchip very late. The obvious solution is what you originally had in your v6, which is to set the ops in kvm_timer_enable(), but to do it over *all* the timer interrupts in order not to break NV is a fairly subtle way(we still want to use the .get_input_level() callback on all timers. I ended up with the following diff, which I folded in the respective patches, meaning that patch 4 can be dropped altogether. Thanks, M. diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index f6d2f0246d057..67b989671b410 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -1106,8 +1106,6 @@ static void timer_context_init(struct kvm_vcpu *vcpu, int timerid) void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) { struct arch_timer_cpu *timer = vcpu_timer(vcpu); - struct timer_map map; - struct irq_ops *ops; for (int i = 0; i < NR_KVM_TIMERS; i++) timer_context_init(vcpu, i); @@ -1121,15 +1119,6 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) hrtimer_setup(&timer->bg_timer, kvm_bg_timer_expire, CLOCK_MONOTONIC, HRTIMER_MODE_ABS_HARD); - - get_timer_map(vcpu, &map); - - ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : - &arch_timer_irq_ops; - - kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_vtimer), ops); - if (map.direct_ptimer) - kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_ptimer), ops); } /* @@ -1600,6 +1589,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) { struct arch_timer_cpu *timer = vcpu_timer(vcpu); struct timer_map map; + struct irq_ops *ops; int ret; if (timer->enabled) @@ -1620,6 +1610,12 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) get_timer_map(vcpu, &map); + ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : + &arch_timer_irq_ops; + + for (int i = 0; i < nr_timers(vcpu); i++) + kvm_vgic_set_irq_ops(vcpu, timer_irq(vcpu_get_timer(vcpu, i)), ops); + ret = kvm_vgic_map_phys_irq(vcpu, map.direct_vtimer->host_timer_irq, timer_irq(map.direct_vtimer)); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index e7d07752143be..36410f7cd2ad3 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -526,6 +526,15 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO; + /* Set up the timer */ + kvm_timer_vcpu_init(vcpu); + + kvm_pmu_vcpu_init(vcpu); + + kvm_arm_pvtime_vcpu_init(&vcpu->arch); + + vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu; + /* * This vCPU may have been created after mpidr_data was initialized. * Throw out the pre-computed mappings if that is the case which forces @@ -537,15 +546,6 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) if (err) return err; - /* Set up the timer */ - kvm_timer_vcpu_init(vcpu); - - kvm_pmu_vcpu_init(vcpu); - - kvm_arm_pvtime_vcpu_init(&vcpu->arch); - - vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu; - err = kvm_share_hyp(vcpu, vcpu + 1); if (err) kvm_vgic_vcpu_destroy(vcpu); -- Without deviation from the norm, progress is not possible.