From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2064C38142 for ; Tue, 24 Jan 2023 09:32:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=D+5iN3SnDpbraFvC0BYx64FHyJj8TAdkdmrByO3Vb+E=; b=UeMrC/8KjccodI GAThmrxgYPWz7zvaftlToPlQVq3uqlCgQzFPGfl2FFKc/+Qkd+qL76Ztkz/nEow6aZklFdMRWVr6m KpVaBpR1+Cucjv9KfD5yqpB6ds2bzepF9OJTZ72h8wjjrnQiPQuS56OqhJI730PHrdQjUDY8xI7Qd bhckLyxbY5CngGH5tTedNTnG72AoZ4tACie3SCHo+zT4KqU4Ewx9uE6HAmUqhdQHOHEMqbtuKXWVJ DIY1cB0WUjVaWevlK+GUFgFPFp+BzOeRCYUk/HtMHQ4mAvxAOlTTUlNf4IM+8RjmYQTCBeu8+guhA EO6X9wpWDcSDSAfuebcg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKFeD-002wMt-KA; Tue, 24 Jan 2023 09:31:23 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKFe1-002wKW-4u for linux-arm-kernel@lists.infradead.org; Tue, 24 Jan 2023 09:31:11 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BE3A7B81101; Tue, 24 Jan 2023 09:31:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A6E8C433EF; Tue, 24 Jan 2023 09:31:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674552666; bh=3tLWh9plWhx/zx+qYBQxpCsfutRUp+F8i5P6qrMHuh0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=IgE5ilNMvidZe1AoLoCyGU0fjzJp7wv4yI030zB+ZJ38vhiIXIUBRnCDP3d/fshXs h9uo/JovtHts2unG1RxlHspE2NwCX2L6zbMaYLgYcuLTnulqiNUWSTZHBQVj6+wLaT dvtyazZzHS1GzQHwzCspftPQJJGNWDb0FUH33JmVI1aPDfGZqb2vIz6jLMrgkeHF6H 29mb99rbEFg8cxliXmqaDu8turAcNUVQvepaU3fW3kYYMEvSJXB12usJuReCtr+Y5k quhDpbEzhhQDU6KTE9w3nRjDpifDA5BiI8GADk/whhmbUTGMSPK7Z0PgUxJDwxxLLq Kkyt4/fn5y//Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pKFdw-004CTF-8l; Tue, 24 Jan 2023 09:31:04 +0000 Date: Tue, 24 Jan 2023 09:31:04 +0000 Message-ID: <868rhsmg87.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org Subject: Re: [PATCH 3/4] arm64: add ARM64_HAS_GIC_PRIO_NO_PMHE cpucap In-Reply-To: References: <20230123124042.718743-1-mark.rutland@arm.com> <20230123124042.718743-4-mark.rutland@arm.com> <86bkmpmlkc.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230124_013109_508224_F23E4310 X-CRM114-Status: GOOD ( 38.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 23 Jan 2023 14:30:17 +0000, Mark Rutland wrote: > > On Mon, Jan 23, 2023 at 01:23:31PM +0000, Marc Zyngier wrote: > > On Mon, 23 Jan 2023 12:40:41 +0000, > > Mark Rutland wrote: > > > > > > When Priority Mask Hint Enable (PMHE) == 0b1, the GIC may use the PMR > > > value to determine whether to signal an IRQ to a PE, and consequently > > > after a change to the PMR value, a DSB SY may be required to ensure that > > > interrupts are signalled to a CPU in finite time. When PMHE == 0b0, > > > interrupts are always signalled to the relevant PE, and all masking > > > occurs locally, without requiring a DSB SY. > > > > > > Since commit: > > > > > > f226650494c6aa87 ("arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear") > > > > > > ... we handle this dynamically: in most cases a static key is used to > > > determine whether to issue a DSB SY, but the entry code must read from > > > ICC_CTLR_EL1 as static keys aren't accessible from plain assembly. > > > > > > It would be much nicer to use an alternative instruction sequence for > > > the DSB, as this would avoid the need to read from ICC_CTLR_EL1 in the > > > entry code, and for most other code this will result in simpler code > > > generation with fewer instructions and fewer branches. > > > > > > This patch adds a new ARM64_HAS_GIC_PRIO_NO_PMHE cpucap which is only > > > set when ICC_CTLR_EL1.PMHE == 0b0 (and GIC priority masking is in use). > > > This allows us to replace the existing users of the `gic_pmr_sync` > > > static key with alternative sequences which default to a DSB SY and are > > > relaxed to a NOP when PMHE is not in use. > > > > I personally find the "negative capability" pretty annoying, specially > > considering that hardly anyone uses PMHE. The way the code reads with > > this patch, it is always some sort of double negation. > > For the polarity and double-negation, I could rename this to > ARM64_HAS_GIC_PRIO_RELAXED_SYNC, if that helps? It certainly reads much better. > > > Can't the DSB be patched-in instead, making the PMHE cap a "positive" > > one? > > We could; my rationale for doing it this way is that we can use the common NOP > patching helper, and avoid generating a copy of the `DSB SY` instruction per > pmr_sync() call (which gets generated near to the call and never gets free, > unlike the alt_instr entries), which adds up quickly when using pseudo-NMIs. Having an equivalent to alt_cb_patch_nops to patch in "DSB SY" would result in similar gains, only less reusable... > > > It shouldn't affect interrupt distribution as long as the > > patching occurs before we take interrupts. For modules, the patching always > > occurs before we can run the module, so this should be equally safe. > > I agree it shouldn't matter either way -- until we've patched in > ARM64_HAS_GIC_PRIO_MASKING alternatives it's not going to matter. > > > The patch otherwise looks OK to me. > > Thanks! > > Do you have a preference between the ARM64_HAS_GIC_PRIO_RELAXED_SYNC or > ARM64_HAS_GIC_PRIO_PMHE options above? ARM64_HAS_GIC_PRIO_PMHE would have my preference (it spells out the feature that drives the property), but this requires a bit more work (a new patching callback), and probably results in more limited gains memory wise. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel