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Thu, 04 Dec 2025 12:06:05 +0000 Date: Thu, 04 Dec 2025 12:06:04 +0000 Message-ID: <86a4zypi37.wl-maz@kernel.org> From: Marc Zyngier To: Ben Horgan Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Yao Yuan Subject: Re: [PATCH v3 8/9] KVM: arm64: pkvm: Report optional ID register traps with a 0x18 syndrome In-Reply-To: <7f853a85-f1da-4e6f-ab3f-63507731f8ee@arm.com> References: <20251204094806.3846619-1-maz@kernel.org> <20251204094806.3846619-9-maz@kernel.org> <7f853a85-f1da-4e6f-ab3f-63507731f8ee@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ben.horgan@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, yaoyuan@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251204_040607_987124_04B3C90B X-CRM114-Status: GOOD ( 25.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 04 Dec 2025 10:51:19 +0000, Ben Horgan wrote: > > Hi Marc, > > On 12/4/25 09:48, Marc Zyngier wrote: > > With FEAT_IDST, unimplemented system registers in the feature ID space > > must be reported using EC=0x18 at the closest handling EL, rather than > > with an UNDEF. > > > > Most of these system registers are always implemented thanks to their > > dependency on FEAT_AA64, except for a set of (currently) three registers: > > GMID_EL1 (depending on MTE2), CCSIDR2_EL1 (depending on FEAT_CCIDX), > > and SMIDR_EL1 (depending on SME). > > > > For these three registers, report their trap as EC=0x18 if they > > end-up trapping into KVM and that FEAT_IDST is implemented in the guest. > > Otherwise, just make them UNDEF. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/hyp/nvhe/sys_regs.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c > > index 876b36d3d4788..efc36645f4b5a 100644 > > --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c > > +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c > > @@ -347,6 +347,18 @@ static bool pvm_gic_read_sre(struct kvm_vcpu *vcpu, > > return true; > > } > > > > +static bool pvm_idst_access(struct kvm_vcpu *vcpu, > > + struct sys_reg_params *p, > > + const struct sys_reg_desc *r) > > +{ > > + if (kvm_has_feat_enum(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, NI)) > > + inject_undef64(vcpu); > > + else > > + inject_sync64(vcpu, kvm_vcpu_get_esr(vcpu)); > > + > > + return false; > > +} > > + > > Just wondering, why is the pkvm version register specific? You changed > the non-pkvm from register specific to generic. Because pKVM relies on a full enumeration of the registers as a design principle, and refrains from having wide-casting nets as a catch-all. That's to ensure that there is a "surprise trap" always results in an UNDEF. Different model from the rest of KVM. Thanks, M. -- Without deviation from the norm, progress is not possible.