From: Marc Zyngier <maz@kernel.org>
To: Fuad Tabba <tabba@google.com>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oupton@kernel.org>,
Zenghui Yu <yuzenghui@huawei.com>,
Christoffer Dall <christoffer.dall@arm.com>,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
Yao Yuan <yaoyuan@linux.alibaba.com>
Subject: Re: [PATCH v2 29/45] KVM: arm64: GICv3: Set ICH_HCR_EL2.TDIR when interrupts overflow LR capacity
Date: Fri, 14 Nov 2025 17:41:10 +0000 [thread overview]
Message-ID: <86a50otsuh.wl-maz@kernel.org> (raw)
In-Reply-To: <CA+EHjTzi9Q9hqAu1Xk51hO3uz0FdUGjdPSViN4RAD6tuXJkvYQ@mail.gmail.com>
On Fri, 14 Nov 2025 15:53:33 +0000,
Fuad Tabba <tabba@google.com> wrote:
>
> Hi Marc,
>
> On Fri, 14 Nov 2025 at 15:02, Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Fri, 14 Nov 2025 14:20:46 +0000,
> > Fuad Tabba <tabba@google.com> wrote:
> > >
> > > Hi Marc,
> > >
> > > On Sun, 9 Nov 2025 at 17:17, Marc Zyngier <maz@kernel.org> wrote:
> > > >
> > > > Now that we are ready to handle deactivation through ICV_DIR_EL1,
> > > > set the trap bit if we have active interrupts outside of the LRs.
> > > >
> > > > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > > > ---
> > > > arch/arm64/kvm/vgic/vgic-v3.c | 7 +++++++
> > > > 1 file changed, 7 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
> > > > index 1026031f22ff9..26e17ed057f00 100644
> > > > --- a/arch/arm64/kvm/vgic/vgic-v3.c
> > > > +++ b/arch/arm64/kvm/vgic/vgic-v3.c
> > > > @@ -42,6 +42,13 @@ void vgic_v3_configure_hcr(struct kvm_vcpu *vcpu,
> > > > ICH_HCR_EL2_VGrp0DIE : ICH_HCR_EL2_VGrp0EIE;
> > > > cpuif->vgic_hcr |= (cpuif->vgic_vmcr & ICH_VMCR_ENG1_MASK) ?
> > > > ICH_HCR_EL2_VGrp1DIE : ICH_HCR_EL2_VGrp1EIE;
> > > > +
> > > > + /*
> > > > + * Note that we set the trap irrespective of EOIMode, as that
> > > > + * can change behind our back without any warning...
> > > > + */
> > > > + if (irqs_active_outside_lrs(als))
> > > > + cpuif->vgic_hcr |= ICH_HCR_EL2_TDIR;
> > > > }
> > >
> > > I just tested these patches as they are on kvmarm/next
> > > 2ea7215187c5759fc5d277280e3095b350ca6a50 ("Merge branch
> > > 'kvm-arm64/vgic-lr-overflow' into kvmarm/next"), without any
> > > additional pKVM patches. I tried running it with pKVM (non-protected)
> > > and with just plain nVHE. In both cases, I get a trap to EL2 (0x18)
> > > when booting a non-protected guest, which triggers a bug in
> > > handle_trap() arch/arm64/kvm/hyp/nvhe/hyp-main.c:706
> > >
> > > This trap is happening because of setting this particular trap (TDIR).
> > > Just removing this trap from vgic_v3_configure_hcr() from the ToT on
> > > kvmarm/next boots fine.
> >
> > This is surprising, as I'm not hitting this on actual HW. Are you
> > getting a 0x18 trap? If so, is it coming from the host? Can you
> > correlate the PC with what the host is doing?
>
> I should have given you that earlier, sorry.
>
> Yes, it's an 0x18 trap from the host (although it happens when I boot
> a guest). Here is the relevant part of the backtrace addr2lined and
> the full one below.
>
> handle_percpu_devid_irq+0x90/0x120 (kernel/irq/chip.c:930)
> generic_handle_domain_irq+0x40/0x64 (include/linux/irqdesc.h:?)
> gic_handle_irq+0x4c/0x110 (include/linux/irqdesc.h:?)
> call_on_irq_stack+0x30/0x48 (arch/arm64/kernel/entry.S:893)
>
> [ 28.454804] Code: d65f03c0 92800008 f9000008 17fffffa (d4210000)
> [ 28.454873] kvm [266]: Hyp Offset: 0xfff1205c3fe00000
> [ 28.455157] Kernel panic - not syncing: HYP panic:
> [ 28.455157] PS:204023c9 PC:000e5fa4413e39bc ESR:00000000f2000800
> [ 28.455157] FAR:ffff800082733d3c HPFAR:0000000000500000 PAR:0000000000000000
I expect you have a write to ICC_DIR_EL1 at this address?
> [ 28.455157] VCPU:0000000000000000
> [ 28.459703] CPU: 5 UID: 0 PID: 266 Comm: kvm-vcpu-0 Not tainted
> 6.18.0-rc3-g2ea7215187c5 #8 PREEMPT
> [ 28.460247] Hardware name: linux,dummy-virt (DT)
> [ 28.460615] Call trace:
> [ 28.460900] show_stack+0x18/0x24 (C)
> [ 28.461234] dump_stack_lvl+0x40/0x84
> [ 28.461421] dump_stack+0x18/0x24
> [ 28.461566] vpanic+0x11c/0x364
> [ 28.461698] vpanic+0x0/0x364
> [ 28.461838] nvhe_hyp_panic_handler+0x118/0x190
> [ 28.462056] handle_percpu_devid_irq+0x90/0x120
> [ 28.462248] handle_percpu_devid_irq+0x90/0x120
> [ 28.462439] generic_handle_domain_irq+0x40/0x64
> [ 28.462643] gic_handle_irq+0x4c/0x110
> [ 28.462814] call_on_irq_stack+0x30/0x48
> [ 28.463003] do_interrupt_handler+0x4c/0x6c
> [ 28.463184] el1_interrupt+0x3c/0x60
> [ 28.463348] el1h_64_irq_handler+0x18/0x24
> [ 28.463525] el1h_64_irq+0x6c/0x70
> [ 28.463799] local_daif_restore+0x8/0xc (P)
> [ 28.463980] el0t_64_sync_handler+0x84/0x12c
> [ 28.464164] el0t_64_sync+0x198/0x19c
>
> > It would indicate that we are leaking trap bits on exit, and that QEMU
> > is trapping ICC_DIR_EL1 on top of ICV_DIR_EL1 (which the HW I have
> > access to doesn't seem to do).
> >
> > > I'm running this on QEMU with '-machine virt,gic-version=3 -cpu max'
> > > and the kernel with 'kvm-arm.mode=protected' and with
> > > 'kvm-arm.mode=nvhe'.
> > >
> > > Let me know if you need any more info or help testing.
> >
> > On top of the above, could you give the hack below a go? I haven't
> > tested it at all (I'm in the middle of a bisect from hell...)
>
> With the hack it boots, both nvhe and protected mode.
OK. At least we know what the issue is, and it shouldn't be too hard
to fix. I guess there is an opportunity for cleanup here, and I'll
look into it shortly (probably not before Monday though).
Thanks again,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-11-14 17:41 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-09 17:15 [PATCH v2 00/45] KVM: arm64: Add LR overflow infrastructure Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 01/45] irqchip/gic: Add missing GICH_HCR control bits Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 02/45] irqchip/gic: Expose CPU interface VA to KVM Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 03/45] irqchip/apple-aic: Spit out ICH_MISR_EL2 value on spurious vGIC MI Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 04/45] KVM: arm64: Turn vgic-v3 errata traps into a patched-in constant Marc Zyngier
2025-11-10 10:40 ` Suzuki K Poulose
2025-11-10 11:47 ` Marc Zyngier
2025-11-11 23:53 ` Oliver Upton
2025-11-13 9:52 ` Marek Szyprowski
2025-11-13 10:56 ` Marc Zyngier
2025-11-13 11:04 ` Marek Szyprowski
2025-11-13 11:23 ` Joey Gouly
2025-11-13 11:42 ` Marc Zyngier
2025-11-13 10:59 ` Marc Zyngier
2025-11-13 11:20 ` Marek Szyprowski
2025-11-13 18:01 ` Mark Brown
2025-11-14 9:37 ` Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 05/45] KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping Marc Zyngier
2025-11-13 14:33 ` Mark Brown
2025-11-13 18:15 ` Marc Zyngier
2025-11-13 19:06 ` Mark Brown
2025-11-13 20:10 ` Marc Zyngier
2025-11-13 21:59 ` Oliver Upton
2025-11-09 17:15 ` [PATCH v2 06/45] KVM: arm64: Repack struct vgic_irq fields Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 07/45] KVM: arm64: Add tracking of vgic_irq being present in a LR Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 08/45] KVM: arm64: Add LR overflow handling documentation Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 09/45] KVM: arm64: GICv3: Drop LPI active state when folding LRs Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 10/45] KVM: arm64: GICv3: Preserve EOIcount on exit Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 11/45] KVM: arm64: GICv3: Decouple ICH_HCR_EL2 programming from LRs Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 12/45] KVM: arm64: GICv3: Extract LR folding primitive Marc Zyngier
2025-11-10 9:01 ` Yao Yuan
2025-11-10 9:18 ` Marc Zyngier
2025-11-10 9:48 ` Yao Yuan
2025-11-09 17:15 ` [PATCH v2 13/45] KVM: arm64: GICv3: Extract LR computing primitive Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 14/45] KVM: arm64: GICv2: Preserve EOIcount on exit Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 15/45] KVM: arm64: GICv2: Decouple GICH_HCR programming from LRs being loaded Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 16/45] KVM: arm64: GICv2: Extract LR folding primitive Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 17/45] KVM: arm64: GICv2: Extract LR computing primitive Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 18/45] KVM: arm64: Compute vgic state irrespective of the number of interrupts Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 19/45] KVM: arm64: Eagerly save VMCR on exit Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 20/45] KVM: arm64: Revamp vgic maintenance interrupt configuration Marc Zyngier
2025-11-12 0:08 ` Oliver Upton
2025-11-12 8:33 ` Marc Zyngier
2025-11-12 8:45 ` Oliver Upton
2025-11-12 9:56 ` Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 21/45] KVM: arm64: Turn kvm_vgic_vcpu_enable() into kvm_vgic_vcpu_reset() Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 22/45] KVM: arm64: Make vgic_target_oracle() globally available Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 23/45] KVM: arm64: Invert ap_list sorting to push active interrupts out Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 24/45] KVM: arm64: Move undeliverable interrupts to the end of ap_list Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 25/45] KVM: arm64: Use MI to detect groups being enabled/disabled Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 26/45] KVM: arm64: GICv3: Handle LR overflow when EOImode==0 Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 27/45] KVM: arm64: GICv3: Handle deactivation via ICV_DIR_EL1 traps Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 28/45] KVM: arm64: GICv3: Add GICv2 SGI handling to deactivation primitive Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 29/45] KVM: arm64: GICv3: Set ICH_HCR_EL2.TDIR when interrupts overflow LR capacity Marc Zyngier
2025-11-14 14:20 ` Fuad Tabba
2025-11-14 15:02 ` Marc Zyngier
2025-11-14 15:53 ` Fuad Tabba
2025-11-14 17:41 ` Marc Zyngier [this message]
2025-11-17 8:22 ` Fuad Tabba
2025-11-17 11:56 ` Marc Zyngier
2025-11-24 11:52 ` Mark Brown
2025-11-24 13:06 ` Marc Zyngier
2025-11-24 13:23 ` Mark Brown
2025-11-24 13:40 ` Marc Zyngier
2025-11-24 14:12 ` Marc Zyngier
2025-11-24 15:06 ` Mark Brown
2025-11-09 17:16 ` [PATCH v2 30/45] KVM: arm64: GICv3: Add SPI tracking to handle asymmetric deactivation Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 31/45] KVM: arm64: GICv3: Handle in-LR deactivation when possible Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 32/45] KVM: arm64: GICv3: Avoid broadcast kick on CPUs lacking TDIR Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 33/45] KVM: arm64: GICv2: Handle LR overflow when EOImode==0 Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 34/45] KVM: arm64: GICv2: Handle deactivation via GICV_DIR traps Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 35/45] KVM: arm64: GICv2: Always trap GICV_DIR register Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 36/45] KVM: arm64: selftests: gic_v3: Add irq group setting helper Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 37/45] KVM: arm64: selftests: gic_v3: Disable Group-0 interrupts by default Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 38/45] KVM: arm64: selftests: vgic_irq: Fix GUEST_ASSERT_IAR_EMPTY() helper Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 39/45] KVM: arm64: selftests: vgic_irq: Change configuration before enabling interrupt Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 40/45] KVM: arm64: selftests: vgic_irq: Exclude timer-controlled interrupts Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 41/45] KVM: arm64: selftests: vgic_irq: Remove LR-bound limitation Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 42/45] KVM: arm64: selftests: vgic_irq: Perform EOImode==1 deactivation in ack order Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 43/45] KVM: arm64: selftests: vgic_irq: Add asymmetric SPI deaectivation test Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 44/45] KVM: arm64: selftests: vgic_irq: Add Group-0 enable test Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 45/45] KVM: arm64: selftests: vgic_irq: Add timer deactivation test Marc Zyngier
2025-11-12 9:13 ` [PATCH v2 00/45] KVM: arm64: Add LR overflow infrastructure Oliver Upton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86a50otsuh.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=Volodymyr_Babchuk@epam.com \
--cc=christoffer.dall@arm.com \
--cc=joey.gouly@arm.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=oupton@kernel.org \
--cc=suzuki.poulose@arm.com \
--cc=tabba@google.com \
--cc=yaoyuan@linux.alibaba.com \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).