Re: [PATCH 05/33] KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping

[Marc Zyngier <maz@kernel.org>]

On Wed, 05 Nov 2025 02:01:36 +0000,
kernel test robot <lkp@intel.com> wrote:
> 
> Hi Marc,
> 
> kernel test robot noticed the following build errors:
> 
> [auto build test ERROR on kvmarm/next]
> [also build test ERROR on linus/master v6.18-rc4 next-20251104]
> [cannot apply to arm64/for-next/core tip/irq/core]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
> 
> url:    https://github.com/intel-lab-lkp/linux/commits/Marc-Zyngier/irqchip-gic-Add-missing-GICH_HCR-control-bits/20251104-011133
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git next
> patch link:    https://lore.kernel.org/r/20251103165517.2960148-6-maz%40kernel.org
> patch subject: [PATCH 05/33] KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping
> config: arm64-randconfig-003-20251105 (https://download.01.org/0day-ci/archive/20251105/202511050925.kQxVnIUB-lkp@intel.com/config)
> compiler: aarch64-linux-gcc (GCC) 8.5.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251105/202511050925.kQxVnIUB-lkp@intel.com/reproduce)
> 
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202511050925.kQxVnIUB-lkp@intel.com/
> 
> All errors (new ones prefixed by >>):
> 
>    arch/arm64/kernel/hyp-stub.S: Assembler messages:
> >> arch/arm64/kernel/hyp-stub.S:59: Error: unknown or missing system register name at operand 2 -- `mrs x1,ich_vtr_el2'
> 
> 
> vim +59 arch/arm64/kernel/hyp-stub.S
> 
>     45	
>     46		.align 11
>     47	
>     48	SYM_CODE_START_LOCAL(elx_sync)
>     49		cmp	x0, #HVC_SET_VECTORS
>     50		b.ne	1f
>     51		msr	vbar_el2, x1
>     52		b	9f
>     53	
>     54	1:	cmp	x0, #HVC_FINALISE_EL2
>     55		b.eq	__finalise_el2
>     56	
>     57		cmp	x0, #HVC_GET_ICH_VTR_EL2
>     58		b.ne	2f
>   > 59		mrs	x1, ich_vtr_el2

Ah, ancient assembler that doesn't understand the GICv3 registers...
Oh well, I'll give it the generated encoding instead.

	M.

-- 
Without deviation from the norm, progress is not possible.