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Fri, 21 Mar 2025 09:04:01 +0000 Date: Fri, 21 Mar 2025 09:04:00 +0000 Message-ID: <86bjtun4an.wl-maz@kernel.org> From: Marc Zyngier To: Peter Chen Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, Krzysztof Kozlowski , Fugang Duan Subject: Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support In-Reply-To: References: <20250305053823.2048217-1-peter.chen@cixtech.com> <20250305053823.2048217-6-peter.chen@cixtech.com> <86frj8m4be.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: peter.chen@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, krzysztof.kozlowski@linaro.org, fugang.duan@cixtech.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 20 Mar 2025 09:57:13 +0000, Peter Chen wrote: > > On 25-03-20 09:36:37, Marc Zyngier wrote: > > Peter Chen wrote: > > > > > > + pmu-a520 { > > > + compatible = "arm,cortex-a520-pmu"; > > > + interrupts = ; > > > + }; > > > + > > > + pmu-a720 { > > > + compatible = "arm,cortex-a720-pmu"; > > > + interrupts = ; > > > + }; > > > + > > > + pmu-spe { > > > + compatible = "arm,statistical-profiling-extension-v1"; > > > + interrupts = ; > > > + }; > > > > SPE should follow the same model as the PMU, as each CPU has its own > > SPE implementation, exposing different micro-architectural details. > > > > Hi Marc, > > Thanks for your reply. But there is only one compatible string > "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c, > how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need > to change arm_spe_pmu.c as well? I don't think there is a need to have different compatible. The driver can probe which CPU this is on, and work out the implemented subfeatures from the PMSIDR_EL1 register. New compatible strings are better avoided when there is a way to probe/discover the HW (and in most cases, there is). Note that this equally applies to TRBE, which also explicitly deals with interrupt partitioning and yet only has a single compatible. Please consider adding TRBE support when you repost this series. Thanks, M. -- Without deviation from the norm, progress is not possible.