From: Marc Zyngier <maz@kernel.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: puranjay@kernel.org, "Arnd Bergmann" <arnd@arndb.de>,
"Arnd Bergmann" <arnd@kernel.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
"Sumit Garg" <sumit.garg@linaro.org>,
puranjay12@gmail.com, "Oliver Upton" <oliver.upton@linux.dev>,
"Suzuki K Poulose" <suzuki.poulose@arm.com>,
"Joey Gouly" <joey.gouly@arm.com>,
"Zenghui Yu" <zenghui.yu@linux.dev>
Subject: Re: Supporting KVM_GUESTDBG_BLOCKIRQ or something similar on ARM64
Date: Tue, 29 Oct 2024 09:53:01 +0000 [thread overview]
Message-ID: <86bjz32q2q.wl-maz@kernel.org> (raw)
In-Reply-To: <CAMj1kXEX2TLdYCn3C-AXhfhjOe6cuzOmd0h5MbgXnzi7Q94T3w@mail.gmail.com>
On Tue, 29 Oct 2024 08:52:41 +0000,
Ard Biesheuvel <ardb@kernel.org> wrote:
>
> On Mon, 28 Oct 2024 at 12:23, Marc Zyngier <maz@kernel.org> wrote:
> >
> > > Let's start a discussion about what needs to be done to support this on
> > > arm64.
> >
> > A good start would be to define the semantics of such a flag:
> >
> > - what should it affect? the vcpu you are single-stepping? all vcpu?
> >
> > - should userspace to know that interrupts are pending?
> >
> > - should this result in any effect on the guest's view of time?
> >
> > - what of interactions on the rest of the system (such as devices)?
> >
>
> Sorry to give a handwavy answer here, but approaching this from a
> usability PoV (like what Puranjay is doing), it is really about
> adhering to the principle of least surprise for the user.
>
> So in that sense, it is not really about blocking IRQs at all, as long
> as we step over them rather than into them. How that is achieved is
> not that relevant from the user PoV, and maybe KVM_GUESTDBG_BLOCKIRQ
> is not the right solution for ARM at all.
I definitely sympathise with the goal, but there is no simple way to
let interrupts through while stepping (which is what your "step over"
implies):
- the hypervisor (in general) doesn't interact with the guest delivery
and handling of interrupts -- this is either very opaque (list
registers) or completely invisible (direct injection)
- replacing the step with a breakpoint after the stepped instruction
requires us to decode the guest instructions to handle branching
effects
One possible mechanism would be to:
- while stepping, add breakpoints to the interrupt vectors for the EL
we are stepping (3 breakpoints for any of the 4 possible exception
groups),
- when any interrupt breakpoint hits, clear all 3, place a breakpoint
on the instruction that was about to be single-stepped (pointed to
by SPSR)
- run to completion, until the breakpoint hits
- disable the breakpoint, reinstall the previous 3 interrupt
breakpoints
- single-step, rinse, repeat
But then I'm asking myself the question: why is this KVM's job? It
seems to me that this is what an external debugger would do when
interacting with HW on bare metal.
So can we implement this as part of the debugger's state machine?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2024-10-29 9:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-28 10:53 Supporting KVM_GUESTDBG_BLOCKIRQ or something similar on ARM64 puranjay
2024-10-28 11:23 ` Marc Zyngier
2024-10-29 8:52 ` Ard Biesheuvel
2024-10-29 9:53 ` Marc Zyngier [this message]
2024-10-29 10:00 ` Ard Biesheuvel
2024-10-29 13:57 ` Mark Rutland
2024-10-29 15:36 ` Marc Zyngier
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