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Fri, 02 Aug 2024 11:59:04 +0100 Date: Fri, 02 Aug 2024 11:59:03 +0100 Message-ID: <86bk2b198o.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [RFC 10/10] KVM: arm64: nv: Add new HDFGRTR2_GROUP & HDFGRTR2_GROUP based FGU handling In-Reply-To: References: <20240620065807.151540-1-anshuman.khandual@arm.com> <20240620065807.151540-11-anshuman.khandual@arm.com> <865xu3kh4r.wl-maz@kernel.org> <4d256df7-1ec7-4300-b5c8-355f46c0e869@arm.com> <878qyy35e5.wl-maz@kernel.org> <47dc4299-52cc-4f98-929b-fb86bd9757ae@arm.com> <86tthhi0nz.wl-maz@kernel.org> <86o76c1b8p.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.3 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_035908_057216_BE98509D X-CRM114-Status: GOOD ( 26.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 02 Aug 2024 10:25:44 +0100, Anshuman Khandual wrote: > > On 8/1/24 21:33, Marc Zyngier wrote: > > On Thu, 01 Aug 2024 11:46:22 +0100, > > Anshuman Khandual wrote: [...] > >> + SR_FGT(SYS_SPMACCESSR_EL1, HDFGRTR2, nSPMACCESSR_EL1, 0), > > > > This (and I take it most of the stuff here) is also gated by > > MDCR_EL2.SPM, which is a coarse grained trap. That needs to be > > described as well. For every new register that you add here. > > I did not find a SPM field in MDCR_EL2 either in latest ARM ARM or in > the latest XML. But as per current HDFGRTR2_EL2 description the field > nSPMACCESSR_EL1 is gated by FEAT_SPMU feature, which is being checked > via ID_AA64DFR1_EL1.PMU when required. So could you please give some > more details. I misspelled it. It is MDCR_EL2.EnSPM. And you are completely missing the point. It is not about HDFGRTR2_EL2, but about SPMACCESSR_EL1 (and all its little friends). To convince yourself, just look at the pseudocode for SPMACCESSR_EL1, limited to an EL1 access: elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGRTR2_EL2.nSPMACCESSR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.EnSPM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X[t, 64] = NVMem[0x8E8]; else X[t, 64] = SPMACCESSR_EL1; Can you spot the *TWO* conditions where we take an exception to EL2 with 0x18 as the EC? - One is when HDFGxTR2_EL2.nSPMACCESSR_EL1 == '0': that's a fine grained trap. - The other is when MDCR_EL2.EnSPM == '0': that's a coarse grained trap. Both conditions need to be captured in the various tables in this file, for each and every register that you describe. [...] > > Now, the main issues are that: > > > > - you're missing the coarse grained trapping for all the stuff you > > have just added. It's not a huge amount of work, but you need, for > > each register, to describe what traps apply to it. The fine grained > > stuff is most, but not all of it. There should be enough of it > > already to guide you through it. > > Coarse grained trapping for FEAT_FGT2 based fine grained registers ? Not for FEAT_FGT2. For the registers that FEAT_FGT2 traps. Can you see the difference? > Afraid, did not understand this. Could you please give some pointers > on similar existing code. See above. And if you want some example, just took at the file you are patching already. Look at how MDCR_EL2 conditions the trapping of all the debug, PMU, AMU registers, for example. There is no shortage of them. Thanks, M. -- Without deviation from the norm, progress is not possible.