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Tue, 06 May 2025 15:52:00 +0100 Date: Tue, 06 May 2025 15:51:59 +0100 Message-ID: <86cyclhjw0.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: =?UTF-8?B?TWlrb8WCYWo=?= Lenczewski , ryan.roberts@arm.com, suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, catalin.marinas@arm.com, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, paulmck@kernel.org, mark.rutland@arm.com, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, oliver.upton@linux.dev, baohua@kernel.org, david@redhat.com, ioworker0@gmail.com, jgg@ziepe.ca, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, kevin.tian@intel.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: Re: [RESEND PATCH v6 1/3] arm64: Add BBM Level 2 cpu feature In-Reply-To: <20250506142508.GB1197@willie-the-truck> References: <20250428153514.55772-2-miko.lenczewski@arm.com> <20250428153514.55772-4-miko.lenczewski@arm.com> <20250506142508.GB1197@willie-the-truck> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, miko.lenczewski@arm.com, ryan.roberts@arm.com, suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, catalin.marinas@arm.com, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, paulmck@kernel.org, mark.rutland@arm.com, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, oliver.upton@linux.dev, baohua@kernel.org, david@redhat.com, ioworker0@gmail.com, jgg@ziepe.ca, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, kevin.tian@intel.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250506_075204_598591_CC3F456F X-CRM114-Status: GOOD ( 27.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 06 May 2025 15:25:09 +0100, Will Deacon wrote: >=20 > On Mon, Apr 28, 2025 at 03:35:14PM +0000, Miko=C5=82aj Lenczewski wrote: > > The Break-Before-Make cpu feature supports multiple levels (levels 0-2), > > and this commit adds a dedicated BBML2 cpufeature to test against > > support for, as well as a kernel commandline parameter to optionally > > disable BBML2 altogether. > >=20 > > This is a system feature as we might have a big.LITTLE architecture > > where some cores support BBML2 and some don't, but we want all cores to > > be available and BBM to default to level 0 (as opposed to having cores > > without BBML2 not coming online). > >=20 > > To support BBML2 in as wide a range of contexts as we can, we want not > > only the architectural guarantees that BBML2 makes, but additionally > > want BBML2 to not create TLB conflict aborts. Not causing aborts avoids > > us having to prove that no recursive faults can be induced in any path > > that uses BBML2, allowing its use for arbitrary kernel mappings. > > Support detection of such CPUs. > >=20 > > Signed-off-by: Miko=C5=82aj Lenczewski > > Reviewed-by: Suzuki K Poulose > > Reviewed-by: Ryan Roberts > > --- > > .../admin-guide/kernel-parameters.txt | 3 + > > arch/arm64/Kconfig | 19 +++++ > > arch/arm64/include/asm/cpucaps.h | 2 + > > arch/arm64/include/asm/cpufeature.h | 5 ++ > > arch/arm64/kernel/cpufeature.c | 71 +++++++++++++++++++ > > arch/arm64/kernel/pi/idreg-override.c | 2 + > > arch/arm64/tools/cpucaps | 1 + > > 7 files changed, 103 insertions(+) > >=20 > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Document= ation/admin-guide/kernel-parameters.txt > > index d9fd26b95b34..2749c67a4f07 100644 > > --- a/Documentation/admin-guide/kernel-parameters.txt > > +++ b/Documentation/admin-guide/kernel-parameters.txt > > @@ -449,6 +449,9 @@ > > arm64.no32bit_el0 [ARM64] Unconditionally disable the execution of > > 32 bit applications. > > =20 > > + arm64.nobbml2 [ARM64] Unconditionally disable Break-Before-Make Level > > + 2 support >=20 > Hmm, I'm not sure we really want this. It opens up the door for folks to > pass 'id_aa64mmfr2.bbm=3D2' without updating the allow-list which feels > like it's going to make crashes harder to reason about. Passing id_aa64mmfr2.bbm=3D2 shouldn't have any effect if the HW doesn't advertise it already, as you can only downgrade features. Trying to upgrade features should leave a nastygram in the kernel log. M. --=20 Without deviation from the norm, progress is not possible.