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From: Marc Zyngier <maz@kernel.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v3 0/3] arm64: Drop support for VPIPT i-cache policy
Date: Tue, 05 Dec 2023 11:53:20 +0000	[thread overview]
Message-ID: <86cyvkc1cf.wl-maz@kernel.org> (raw)
In-Reply-To: <ZW8DXGQCSWO1wB2m@FVFF77S0Q05N>

On Tue, 05 Dec 2023 11:03:16 +0000,
Mark Rutland <mark.rutland@arm.com> wrote:
> 
> On Mon, Dec 04, 2023 at 06:26:25PM +0000, Marc Zyngier wrote:
> > How about the patch below (tested in a guest with a bunch of hacks to
> > expose different L1Ip values)?
> 
> That's roughly what I was thinking; the diff looks good, minor comments below.
> 
> [...]
> 
> >  /*
> >   * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
> >   * permitted in the I-cache.
> >   */
> >  static inline int icache_is_aliasing(void)
> >  {
> > -	return test_bit(ICACHEF_ALIASING, &__icache_flags);
> > +	return !cpus_have_cap(ARM64_ICACHE_PIPT);
> >  }
> 
> It might be nicer to use alternative_has_cap_{likely,unlikely}(...) for
> consistency with other cap checks, though that won't matter for hyp code and I
> don't think the likely/unlikely part particularly matters either.

Right, this should be marginally better. I was initially worried of
the cap not being configured yet, but since we start by assuming VIPT
and only flip to PIPT once we have seen all CPUs, this stays correct
by construction.

> [...]
> 
> > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> > index c5af75b23187..db8c96841138 100644
> > --- a/arch/arm64/tools/sysreg
> > +++ b/arch/arm64/tools/sysreg
> > @@ -2003,7 +2003,7 @@ Field	28	IDC
> >  Field	27:24	CWG
> >  Field	23:20	ERG
> >  Field	19:16	DminLine
> > -Enum	15:14	L1Ip
> > +UnsignedEnum	15:14	L1Ip
> >  	# This was named as VPIPT in the ARM but now documented as reserved
> >  	0b00	RESERVED_VPIPT
> >  	# This is named as AIVIVT in the ARM but documented as reserved
> 
> I was initially surprised by the use of UnsignedEnum, but given PIPT is 0b11, I
> can see that works. Otherwise, we can keep this as an enum and use a helper
> that checks for an exact match.

Yeah, I hesitated either way, but maybe the helper approach is
cleaner.  I'll give it a go and repost this patch.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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  reply	other threads:[~2023-12-05 11:53 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-04 14:36 [PATCH v3 0/3] arm64: Drop support for VPIPT i-cache policy Marc Zyngier
2023-12-04 14:36 ` [PATCH v3 1/3] KVM: arm64: Remove VPIPT I-cache handling Marc Zyngier
2023-12-04 14:36 ` [PATCH v3 2/3] arm64: Kill detection of VPIPT i-cache policy Marc Zyngier
2023-12-04 14:36 ` [PATCH v3 3/3] arm64: Rename reserved values for CTR_EL0.L1Ip Marc Zyngier
2023-12-05  2:04   ` Anshuman Khandual
2023-12-04 14:44 ` [PATCH v3 0/3] arm64: Drop support for VPIPT i-cache policy Mark Rutland
2023-12-04 18:26   ` Marc Zyngier
2023-12-05 11:03     ` Mark Rutland
2023-12-05 11:53       ` Marc Zyngier [this message]
2023-12-05 15:16 ` Will Deacon

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