From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90866FED9EF for ; Tue, 17 Mar 2026 18:05:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mwp4/UkuiJZhj3Qsuw2Opr4d531GgSwnHfCxk6uCfck=; b=Pxdxex7ftzfvjSHZbUTPACJDDf ADtlDn8nNxZ4pr2EdbIDHOEaWSyXaaTeiis7UccTAwFx4BHPQnpJAWJejamEKuqqg1dQfkkFEDw/F or/mUTRdZOGMmn9ZMQtAohBwq+5wGfw6dS9mDotEub3fKNYuXjIoxEBbPi26LU+e/LVSzCH+cAuIy Df3JsIQFGC6RTVCsntcnmEqJDGyyZM2m1mHNpEuFTzbGtlUc6meMNuzLH12cYWJpcdeDaeUxc8+Ui JRYG6k4YRpy4V/c2FXIMMRdefFMLrRMbzJ3mepcxMjsxfVJeHAMozZREc6q/hlMl/VQ8hmoU3n8KR 7C2G1X3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w2Ync-000000070cD-3alY; Tue, 17 Mar 2026 18:05:48 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w2YnZ-000000070bw-1rZx for linux-arm-kernel@lists.infradead.org; Tue, 17 Mar 2026 18:05:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 7C7FA600AD; Tue, 17 Mar 2026 18:05:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0921EC4CEF7; Tue, 17 Mar 2026 18:05:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773770744; bh=ESmVPCa9igCBCv1hcJ5QEA7fejdWLwcrCD3qXAO15o8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=QJCgPO37xtZtU0y3XW18rX/Cmsmwx4/gto75ctS4CHkACMaj6lGUG6OJHCe6k/542 DLVq1TnOwg6bGZyAVOndcwHrocPF3bdlSNNaaKXivwDVaJTGFIA9My8OjaHnc9D9mo b6MA/vxH65raRpZccY4KiN3Nd1D4IHF2bjugmW4Kyw9hpHrLmOSOgq8J/BBP6VzqUu xHN6lAuMRmO6c1yK5s0pNxDXQ8peEeRrU+iL5J0xW8l1TYqB5XhyFEhO1D8qxZaXdg XE+zX+P1trck0GEpEcpjchOCwfZxp2g8O98ZNhMmnCpGI9kkV6BB7vCmav7pbzxZC+ S8xuoncNvQYLw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w2YnT-00000002xnV-3WJV; Tue, 17 Mar 2026 18:05:39 +0000 Date: Tue, 17 Mar 2026 18:05:39 +0000 Message-ID: <86ecli5o24.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v6 29/39] KVM: arm64: gic-v5: Enlighten arch timer for GICv5 In-Reply-To: <20260317113949.2548118-30-sascha.bischoff@arm.com> References: <20260317113949.2548118-1-sascha.bischoff@arm.com> <20260317113949.2548118-30-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 17 Mar 2026 11:47:29 +0000, Sascha Bischoff wrote: > > Now that GICv5 has arrived, the arch timer requires some TLC to > address some of the key differences introduced with GICv5. > > For PPIs on GICv5, the queue_irq_unlock irq_op is used as AP lists are > not required at all for GICv5. The arch timer also introduces an > irq_op - get_input_level. Extend the arch-timer-provided irq_ops to > include the PPI op for vgic_v5 guests. > > When possible, DVI (Direct Virtual Interrupt) is set for PPIs when > using a vgic_v5, which directly inject the pending state into the > guest. This means that the host never sees the interrupt for the guest > for these interrupts. This has three impacts. > > * First of all, the kvm_cpu_has_pending_timer check is updated to > explicitly check if the timers are expected to fire. > > * Secondly, for mapped timers (which use DVI) they must be masked on > the host prior to entering a GICv5 guest, and unmasked on the return > path. This is handled in set_timer_irq_phys_masked. > > * Thirdly, it makes zero sense to attempt to inject state for a DVI'd > interrupt. Track which timers are direct, and skip the call to > kvm_vgic_inject_irq() for these. > > The final, but rather important, change is that the architected PPIs > for the timers are made mandatory for a GICv5 guest. Attempts to set > them to anything else are actively rejected. Once a vgic_v5 is > initialised, the arch timer PPIs are also explicitly reinitialised to > ensure the correct GICv5-compatible PPIs are used - this also adds in > the GICv5 PPI type to the intid. > > Signed-off-by: Sascha Bischoff > Reviewed-by: Jonathan Cameron > --- > arch/arm64/kvm/arch_timer.c | 110 ++++++++++++++++++++++++++------ > arch/arm64/kvm/vgic/vgic-init.c | 9 +++ > arch/arm64/kvm/vgic/vgic-v5.c | 7 +- > include/kvm/arm_arch_timer.h | 11 +++- > include/kvm/arm_vgic.h | 3 + > 5 files changed, 115 insertions(+), 25 deletions(-) > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 53312b88c342d..4575c36cae537 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -56,6 +56,12 @@ static struct irq_ops arch_timer_irq_ops = { > .get_input_level = kvm_arch_timer_get_input_level, > }; > > +static struct irq_ops arch_timer_irq_ops_vgic_v5 = { > + .get_input_level = kvm_arch_timer_get_input_level, > + .queue_irq_unlock = vgic_v5_ppi_queue_irq_unlock, > + .set_direct_injection = vgic_v5_set_ppi_dvi, > +}; > + > static int nr_timers(struct kvm_vcpu *vcpu) > { > if (!vcpu_has_nv(vcpu)) > @@ -177,6 +183,10 @@ void get_timer_map(struct kvm_vcpu *vcpu, struct timer_map *map) > map->emul_ptimer = vcpu_ptimer(vcpu); > } > > + map->direct_vtimer->direct = true; > + if (map->direct_ptimer) > + map->direct_ptimer->direct = true; > + > trace_kvm_get_timer_map(vcpu->vcpu_id, map); > } > > @@ -396,7 +406,11 @@ static bool kvm_timer_should_fire(struct arch_timer_context *timer_ctx) > > int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) > { > - return vcpu_has_wfit_active(vcpu) && wfit_delay_ns(vcpu) == 0; > + struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); > + struct arch_timer_context *ptimer = vcpu_ptimer(vcpu); > + > + return kvm_timer_should_fire(vtimer) || kvm_timer_should_fire(ptimer) || > + (vcpu_has_wfit_active(vcpu) && wfit_delay_ns(vcpu) == 0); > } > > /* > @@ -447,6 +461,10 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, > if (userspace_irqchip(vcpu->kvm)) > return; > > + /* Skip injecting on GICv5 for directly injected (DVI'd) timers */ > + if (vgic_is_v5(vcpu->kvm) && timer_ctx->direct) > + return; > + > kvm_vgic_inject_irq(vcpu->kvm, vcpu, > timer_irq(timer_ctx), > timer_ctx->irq.level, > @@ -657,6 +675,24 @@ static inline void set_timer_irq_phys_active(struct arch_timer_context *ctx, boo > WARN_ON(r); > } > > +/* > + * On GICv5 we use DVI for the arch timer PPIs. This is restored later > + * on as part of vgic_load. Therefore, in order to avoid the guest's > + * interrupt making it to the host we mask it before entering the > + * guest and unmask it again when we return. > + */ > +static inline void set_timer_irq_phys_masked(struct arch_timer_context *ctx, bool masked) > +{ > + if (masked) { > + disable_percpu_irq(ctx->host_timer_irq); > + } else { > + if (ctx->host_timer_irq == host_vtimer_irq) > + enable_percpu_irq(ctx->host_timer_irq, host_vtimer_irq_flags); > + else > + enable_percpu_irq(ctx->host_timer_irq, host_ptimer_irq_flags); > + } > +} I think this is missing a trick, which is to reuse the mask/unmask infrastructure we use for the fruity crap. How about this following untested hack? diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 600f250753b45..b29bea800e2ab 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -660,7 +660,7 @@ static inline void set_timer_irq_phys_active(struct arch_timer_context *ctx, boo static void kvm_timer_vcpu_load_gic(struct arch_timer_context *ctx) { struct kvm_vcpu *vcpu = timer_context_to_vcpu(ctx); - bool phys_active = false; + bool phys_active = vgic_is_v5(vcpu->kvm); /* * Update the timer output so that it is likely to match the @@ -934,6 +934,12 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) if (kvm_vcpu_is_blocking(vcpu)) kvm_timer_blocking(vcpu); + + if (vgic_is_v5(vcpu)) { + set_timer_irq_phys_active(map.direct_vtimer, false); + if (map.direct_ptimer) + set_timer_irq_phys_active(map.direct_ptimer, false); + } } void kvm_timer_sync_nested(struct kvm_vcpu *vcpu) @@ -1333,7 +1339,8 @@ static int kvm_irq_init(struct arch_timer_kvm_info *info) host_vtimer_irq = info->virtual_irq; kvm_irq_fixup_flags(host_vtimer_irq, &host_vtimer_irq_flags); - if (kvm_vgic_global_state.no_hw_deactivation) { + if (kvm_vgic_global_state.no_hw_deactivation || + kvm_vgic_global_state.type == VGIC_V5) { struct fwnode_handle *fwnode; struct irq_data *data; @@ -1351,7 +1358,8 @@ static int kvm_irq_init(struct arch_timer_kvm_info *info) return -ENOMEM; } - arch_timer_irq_ops.flags |= VGIC_IRQ_SW_RESAMPLE; + if (kvm_vgic_global_state.no_hw_deactivation) + arch_timer_irq_ops.flags |= VGIC_IRQ_SW_RESAMPLE; WARN_ON(irq_domain_push_irq(domain, host_vtimer_irq, (void *)TIMER_VTIMER)); } which should avoid adding some new masking stuff. Thanks, M. -- Without deviation from the norm, progress is not possible.