From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07B3FC3DA49 for ; Fri, 2 Aug 2024 10:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vfWchaaK/4w+Iqm9O/FZgy63Qbt7dDuX+C7BEevn7/g=; b=f9svdfsoHmH7knl6UdArYHUMzS IrLhsKBcp/zmIwTPx35q2il0Ks1Homni5Vp/2/NXDttpuF/L7zYHMgyPezh2CYGqkBWdM8xiPwdfE v1EMU4pOZtSWFuS5cJfnIsoRkbpk7JJZBk17HMNoinRdTGNoGPh4NrjCCLByqMAmlLYxFNsb+oymG JbYAjkqJ/ppBAsyYNRvmeEd/GnpD0b7wLE+CDQeeNvZNDDVI/qkwbYx6GiF66Y6bwTghk4rTulsrI LEuXg7mrjs0VNXEKCJGbXVy3BeWMS0EYL1DKg0MJCeeIjIv3FhvNUBoVNlBuHWwHx7q5jrMlKa3vx fDxTHWNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZpfN-00000008VK6-05oF; Fri, 02 Aug 2024 10:37:45 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZpeq-00000008VBZ-39rv for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2024 10:37:14 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id CA58DCE16E6; Fri, 2 Aug 2024 10:37:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C63FC32782; Fri, 2 Aug 2024 10:37:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722595030; bh=YKYTZsd6PA5EsfUaV9bE9bWVqUgRVY4cdcNVx/H78v8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ejBeBDybee/EC/6BWz3t4jmgARbLlJEafQ20citmJd/2ALSN3am8r5JwG+7yR+3/r Zsq3svFV6Qh9bDZ1sqlwN8/uvEQBQufseGKLbJisERjAkI51e0Mwl7ByHusnyGHQuq Y63j0ChRWdb2pQq+rzfzTLXunEmAF8RqB9gpkUCRCyPwOQ5J7k0jf0ya6yvU8KSbeN hf0ukxqEbxZ0kC7Pq7Lz4FF4Yi3gXd12C5EE17dD4P+SdN8kUDg/QxKMIkU4ERDnFf yMoMU09SGA7vNOvfkYmQGRfowazdvpd+QUw56H6iTNE2g5jqwxv3jvRMV2DuMOkmuU Jqwk0VDm+lR7w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sZpem-0005C7-6w; Fri, 02 Aug 2024 11:37:08 +0100 Date: Fri, 02 Aug 2024 11:37:07 +0100 Message-ID: <86ed771a98.wl-maz@kernel.org> From: Marc Zyngier To: Yicong Yang Cc: , , , , , , , , , , , , , Subject: Re: [PATCH 1/2] arm64: Add support for FEAT_HAFT In-Reply-To: <20240802093458.32683-2-yangyicong@huawei.com> References: <20240802093458.32683-1-yangyicong@huawei.com> <20240802093458.32683-2-yangyicong@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.3 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: yangyicong@huawei.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, broonie@kernel.org, ryan.roberts@arm.com, linuxarm@huawei.com, jonathan.cameron@huawei.com, shameerali.kolothum.thodi@huawei.com, prime.zeng@hisilicon.com, xuwei5@huawei.com, wangkefeng.wang@huawei.com, yangyicong@hisilicon.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_033713_243264_E76822C0 X-CRM114-Status: GOOD ( 35.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 02 Aug 2024 10:34:57 +0100, Yicong Yang wrote: > > From: Yicong Yang > > Armv8.9/v9.4 introduces the feature Hardware managed Access Flag > for Table descriptors (FEAT_HAFT). The feature is indicated by > ID_AA64MMFR1_EL1.HAFDBS == 0b0011 and can be enabled by > TCR2_EL1.HAFT so it has a dependency on FEAT_TCR2. > > This patch adds the Kconfig for FEAT_HAFT and support detecting > and enabling the feature. > > Signed-off-by: Yicong Yang > --- > arch/arm64/Kconfig | 20 ++++++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 5 ++++ > arch/arm64/kernel/cpufeature.c | 38 ++++++++++++++++++++++++++ > arch/arm64/tools/cpucaps | 1 + > arch/arm64/tools/sysreg | 1 + > 5 files changed, 65 insertions(+) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b3fc891f1544..f263ae4139a5 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -2127,6 +2127,26 @@ config ARM64_EPAN > if the cpu does not implement the feature. > endmenu # "ARMv8.7 architectural features" > > +menu "ARMv8.9 architectural features" > + > +config ARM64_HAFT > + bool "Support for Hardware managed Access Flag for Table Descriptor" > + depends on ARM64_HW_AFDBM > + default y > + help > + The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access > + Flag for Table descriptors. When enabled in TCR_EL1 (HAFT bit) on TCR2_EL{1,2}. But I don't think we need to details registers and bit layout in the help section. > + capable processors, an architectural executed memory access will > + update the Access Flag in each Table descriptor which is accessed > + during the translation table walk and for which the Access Flag is > + 0. The Access Flag of the Table descriptor use the same bit of > + PTE_AF. > + > + The feature will only be enabled on supported CPUs. If unsure, > + say Y. > + > +endmenu # "ARMv8.9 architectural features" > + > config ARM64_SVE > bool "ARM Scalable Vector Extension support" > default y > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 1f60aa1bc750..47bd29874e62 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -308,6 +308,11 @@ > #define TCR_TCMA1 (UL(1) << 58) > #define TCR_DS (UL(1) << 59) > > +/* > + * TCR2 Flags > + */ > +#define TCR2_HAFT (UL(1) << 11) > + TCR2_ELx is already fully described in arch/arm64/tools/sysreg. > /* > * TTBR. > */ > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 646ecd3069fd..99402fd00f16 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2044,6 +2044,29 @@ static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, > > #endif > > +#if CONFIG_ARM64_HAFT > + > +static void cpu_enable_haft(struct arm64_cpu_capabilities const *cap) > +{ > + u64 reg = read_sysreg_s(SYS_TCR2_EL1); > + > + reg |= TCR2_HAFT; > + write_sysreg_s(reg, SYS_TCR2_EL1); Probably more elegantly written as sysreg_clear_set_s(SYS_TCR2_EL1, 0, TCR2_EL1x_HAFT); > + isb(); > + local_flush_tlb_all(); > +} > + > +static bool has_haft(const struct arm64_cpu_capabilities *cap, int scope) > +{ > + /* FEAT_HAFT relies on FEAT_TCR2 */ > + if (!this_cpu_has_cap(ARM64_HAS_TCR2)) > + return false; Why do we need this? If FEAT_TCR2 isn't implemented, this is a HW bug. > + > + return has_cpuid_feature(cap, scope); > +} > + > +#endif > + > #ifdef CONFIG_ARM64_AMU_EXTN > > /* > @@ -2580,6 +2603,21 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .cpus = &dbm_cpus, > ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) > }, > +#endif > +#ifdef CONFIG_ARM64_HAFT > + { > + .desc = "Hardware managed Access Flag for Table Descriptor", > + /* > + * Per Spec, software management of Access Flag for Table > + * descriptor is not supported, so make this feature system > + * wide. > + */ I don't understand what you mean by this. Can you please clarify? > + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, > + .capability = ARM64_HAFT, > + .matches = has_haft, > + .cpu_enable = cpu_enable_haft, > + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) > + }, > #endif > { > .desc = "CRC32 instructions", > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index ac3429d892b9..0b7a3a237e5d 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -55,6 +55,7 @@ HAS_TLB_RANGE > HAS_VA52 > HAS_VIRT_HOST_EXTN > HAS_WFXT > +HAFT > HW_DBM > KVM_HVHE > KVM_PROTECTED_MODE > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 7ceaa1e0b4bc..9b3d15ea8a63 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1688,6 +1688,7 @@ UnsignedEnum 3:0 HAFDBS > 0b0000 NI > 0b0001 AF > 0b0010 DBM > + 0b0011 HAFT > EndEnum > EndSysreg > Thanks, M. -- Without deviation from the norm, progress is not possible.