From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCFF6C63797 for ; Tue, 10 Jan 2023 10:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YzD/JEfaxtpyNpAc7cn81AmNoOS9XdlX+tHlaoMAy4c=; b=us4NaE0zqek4ER j6l1KNg9V9apBy9jE7TRkgCrVLWECB7NTlUeHydnps5XvbE8llnbkxZ7ht25+G1LW0lI+muWBWLNi cg8ucggwjKVWvtSOihsY1pmF5wkWZyWQruN571Z/xlKrwxoVsZ6rKpRjtqxCSZLpvQIVttdOweQWt rJcA2/YUfHReIgby5RpuIuyBpejwsfgkCnpaaJ3H8AjbxEY0lFKhTtXTzehSlrVt971c7aJ1ErBDc X3uCf51RrySSZtq4seRs4UZ/RlLgWLbO1cZ0Bnh4IdM6kW6QHK7jvnulSimuWbHEMerIGFD566uKJ 5A0FQ+61yRi6N2cWJ8Sg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pFC9b-006Ppk-O2; Tue, 10 Jan 2023 10:46:51 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pFC9X-006Pna-Te for linux-arm-kernel@lists.infradead.org; Tue, 10 Jan 2023 10:46:49 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C0F4F615C3; Tue, 10 Jan 2023 10:46:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D7A5C433EF; Tue, 10 Jan 2023 10:46:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673347605; bh=IwaYiwFt7AxkOPmQ2NHjfx6XV8JKYTo6odGCrjg6Sw8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Kf/XCNVNA0zGDtNhrBELxdvyulEIQmRdLtqBT0aibVJKbORt1vQyNR4ytV+jBz6+H uamjltERF+HyQbI8AUMA1B8Ry+hcBqEkaubkM0gTi5TnK1S4dcBZbmFpJjp/zCMoAZ 4Vt0U8ssDUZ/yMgMhivUdwkIuUvK1WJ2Ji2U3wuxzVBEsGug+Crh0hDp4eUYlGfceI MP0g+RldytehbVKdZ3hBu/IPwAeylXjxZqgTRuxB0+1kHupqFJ2xYBLm5jM7kGLBTa TlPt6Yo6bTgp/SpmFi1DkbB6qJV0aGhTKOd1y47+1w1pIn5Qlj9KS5RAWXt1nbTkee rUcJOaSOAxwgw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pFC9S-000YQY-TL; Tue, 10 Jan 2023 10:46:43 +0000 Date: Tue, 10 Jan 2023 10:46:42 +0000 Message-ID: <86eds2oeel.wl-maz@kernel.org> From: Marc Zyngier To: Ganapatrao Kulkarni Cc: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, scott@os.amperecomputing.com, keyur@os.amperecomputing.com Subject: Re: [PATCH 2/3] KVM: arm64: nv: Emulate ISTATUS when emulated timers are fired. In-Reply-To: <31e49612-443b-888a-9730-f4e017251130@os.amperecomputing.com> References: <20220824060304.21128-1-gankulkarni@os.amperecomputing.com> <20220824060304.21128-3-gankulkarni@os.amperecomputing.com> <87y1qqe2pg.wl-maz@kernel.org> <867cy5b1mq.wl-maz@kernel.org> <31e49612-443b-888a-9730-f4e017251130@os.amperecomputing.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: gankulkarni@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, scott@os.amperecomputing.com, keyur@os.amperecomputing.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230110_024648_082358_70529AB5 X-CRM114-Status: GOOD ( 48.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 10 Jan 2023 08:41:44 +0000, Ganapatrao Kulkarni wrote: > > > On 02-01-2023 05:16 pm, Marc Zyngier wrote: > > On Thu, 29 Dec 2022 13:53:15 +0000, > > Marc Zyngier wrote: > >> > >> On Wed, 24 Aug 2022 07:03:03 +0100, > >> Ganapatrao Kulkarni wrote: > >>> > >>> Guest-Hypervisor forwards the timer interrupt to Guest-Guest, if it is > >>> enabled, unmasked and ISTATUS bit of register CNTV_CTL_EL0 is set for a > >>> loaded timer. > >>> > >>> For NV2 implementation, the Host-Hypervisor is not emulating the ISTATUS > >>> bit while forwarding the Emulated Vtimer Interrupt to Guest-Hypervisor. > >>> This results in the drop of interrupt from Guest-Hypervisor, where as > >>> Host Hypervisor marked it as an active interrupt and expecting Guest-Guest > >>> to consume and acknowledge. Due to this, some of the Guest-Guest vCPUs > >>> are stuck in Idle thread and rcu soft lockups are seen. > >>> > >>> This issue is not seen with NV1 case since the register CNTV_CTL_EL0 read > >>> trap handler is emulating the ISTATUS bit. > >>> > >>> Adding code to set/emulate the ISTATUS when the emulated timers are fired. > >>> > >>> Signed-off-by: Ganapatrao Kulkarni > >>> --- > >>> arch/arm64/kvm/arch_timer.c | 5 +++++ > >>> 1 file changed, 5 insertions(+) > >>> > >>> diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > >>> index 27a6ec46803a..0b32d943d2d5 100644 > >>> --- a/arch/arm64/kvm/arch_timer.c > >>> +++ b/arch/arm64/kvm/arch_timer.c > >>> @@ -63,6 +63,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, > >>> struct arch_timer_context *timer, > >>> enum kvm_arch_timer_regs treg); > >>> static bool kvm_arch_timer_get_input_level(int vintid); > >>> +static u64 read_timer_ctl(struct arch_timer_context *timer); > >>> static struct irq_ops arch_timer_irq_ops = { > >>> .get_input_level = kvm_arch_timer_get_input_level, > >>> @@ -356,6 +357,8 @@ static enum hrtimer_restart kvm_hrtimer_expire(struct hrtimer *hrt) > >>> return HRTIMER_RESTART; > >>> } > >>> + /* Timer emulated, emulate ISTATUS also */ > >>> + timer_set_ctl(ctx, read_timer_ctl(ctx)); > >> > >> Why should we do that for non-NV2 configurations? > >> > >>> kvm_timer_update_irq(vcpu, true, ctx); > >>> return HRTIMER_NORESTART; > >>> } > >>> @@ -458,6 +461,8 @@ static void timer_emulate(struct arch_timer_context *ctx) > >>> trace_kvm_timer_emulate(ctx, should_fire); > >>> if (should_fire != ctx->irq.level) { > >>> + /* Timer emulated, emulate ISTATUS also */ > >>> + timer_set_ctl(ctx, read_timer_ctl(ctx)); > >>> kvm_timer_update_irq(ctx->vcpu, should_fire, ctx); > >>> return; > >>> } > >> > >> I'm not overly keen on this. Yes, we can set the status bit there. But > >> conversely, the bit will not get cleared when the guest reprograms the > >> timer, and will take a full exit/entry cycle for it to appear. > >> > >> Ergo, the architecture is buggy as memory (the VNCR page) cannot be > >> used to emulate something as dynamic as a timer. > >> > >> It is only with FEAT_ECV that we can solve this correctly by trapping > >> the counter/timer accesses and emulate them for the guest hypervisor. > >> I'd rather we add support for that, as I expect all the FEAT_NV2 > >> implementations to have it (and hopefully FEAT_FGT as well). > > > > So I went ahead and implemented some very basic FEAT_ECV support to > > correctly emulate the timers (trapping the CTL/CVAL accesses). > > > > Performance dropped like a rock (~30% extra overhead) for L2 > > exit-heavy workloads that are terminated in userspace, such as virtio. > > For those workloads, vcpu_{load,put}() in L1 now generate extra traps, > > as we save/restore the timer context, and this is enough to make > > things visibly slower, even on a pretty fast machine. > > > > I managed to get *some* performance back by satisfying CTL/CVAL reads > > very early on the exit path (a pretty common theme with NV). Which > > means we end-up needing something like what you have -- only a bit > > more complete. I came up with the following: > > Yes it is more appropriate, this moves ISTATUS update to single place. > > > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > > index 4945c5b96f05..a198a6211e2a 100644 > > --- a/arch/arm64/kvm/arch_timer.c > > +++ b/arch/arm64/kvm/arch_timer.c > > @@ -450,6 +450,25 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, > > { > > int ret; > > + /* > > + * Paper over NV2 brokenness by publishing the interrupt status > > + * bit. This still results in a poor quality of emulation (guest > > + * writes will have no effect until the next exit). > > + * > > + * But hey, it's fast, right? > > + */ > > + if (vcpu_has_nv2(vcpu) && is_hyp_ctxt(vcpu) && > > + (timer_ctx == vcpu_vtimer(vcpu) || timer_ctx == vcpu_ptimer(vcpu))) { > > + u32 ctl = timer_get_ctl(timer_ctx); > > + > > + if (new_level) > > + ctl |= ARCH_TIMER_CTRL_IT_STAT; > > + else > > + ctl &= ~ARCH_TIMER_CTRL_IT_STAT; > > + > > + timer_set_ctl(timer_ctx, ctl); > > + } > > + > > timer_ctx->irq.level = new_level; > > trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq, > > timer_ctx->irq.level); > > > > which reports the interrupt state in all cases. > > > > Does this work for you? > > This works. > Are you going to pull this diff/patch in to your 6.2-nv tree? or you > want me to send an updated patch? I already have this in the patch titled: KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state and the result gets used by: KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on (not pasting the SHA1s as I'm still fixing a few nits here and there, and the commit IDs will change). Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel