linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/14] ARM: spectre-v2: add PSCI based hardening
Date: Wed, 23 May 2018 08:25:31 +0100	[thread overview]
Message-ID: <86efi2bzpw.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <20180522175717.GT17671@n2100.armlinux.org.uk>

On Tue, 22 May 2018 18:57:18 +0100,
Russell King wrote:
> 
> On Tue, May 22, 2018 at 06:24:13PM +0100, Marc Zyngier wrote:
> > On 21/05/18 12:45, Russell King wrote:
> > > Add PSCI based hardening for cores that require more complex handling in
> > > firmware.
> > > 
> > > Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> > > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > > ---
> > >  arch/arm/mm/proc-v7-bugs.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
> > >  arch/arm/mm/proc-v7.S      | 21 +++++++++++++++++++
> > >  2 files changed, 71 insertions(+)
> > > 
> > > diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
> > > index 65a9b8141f86..0c37e6a2830d 100644
> > > --- a/arch/arm/mm/proc-v7-bugs.c
> > > +++ b/arch/arm/mm/proc-v7-bugs.c
> > > @@ -1,9 +1,12 @@
> > >  // SPDX-License-Identifier: GPL-2.0
> > > +#include <linux/arm-smccc.h>
> > >  #include <linux/kernel.h>
> > > +#include <linux/psci.h>
> > >  #include <linux/smp.h>
> > >  
> > >  #include <asm/cp15.h>
> > >  #include <asm/cputype.h>
> > > +#include <asm/proc-fns.h>
> > >  #include <asm/system_misc.h>
> > >  
> > >  void cpu_v7_bugs_init(void);
> > > @@ -39,6 +42,9 @@ void cpu_v7_ca15_ibe(void)
> > >  #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
> > >  void (*harden_branch_predictor)(void);
> > >  
> > > +extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
> > > +extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
> > > +
> > >  static void harden_branch_predictor_bpiall(void)
> > >  {
> > >  	write_sysreg(0, BPIALL);
> > > @@ -49,6 +55,18 @@ static void harden_branch_predictor_iciallu(void)
> > >  	write_sysreg(0, ICIALLU);
> > >  }
> > >  
> > > +#ifdef CONFIG_ARM_PSCI
> > > +static void call_smc_arch_workaround_1(void)
> > > +{
> > > +	arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
> > > +}
> > > +
> > > +static void call_hvc_arch_workaround_1(void)
> > > +{
> > > +	arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
> > > +}
> > > +#endif
> > > +
> > >  void cpu_v7_bugs_init(void)
> > >  {
> > >  	const char *spectre_v2_method = NULL;
> > > @@ -73,6 +91,38 @@ void cpu_v7_bugs_init(void)
> > >  		spectre_v2_method = "ICIALLU";
> > >  		break;
> > >  	}
> > > +
> > > +#ifdef CONFIG_ARM_PSCI
> > > +	if (psci_ops.smccc_version != SMCCC_VERSION_1_0) {
> > > +		struct arm_smccc_res res;
> > > +
> > > +		switch (psci_ops.conduit) {
> > > +		case PSCI_CONDUIT_HVC:
> > > +			arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
> > > +					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
> > > +			if ((int)res.a0 < 0)
> > > +				break;
> > 
> > I just realised that there is a small, but significant difference
> > between this and the arm64 version: On arm64, we have a table of
> > vulnerable implementations, and we try the mitigation on a per-cpu
> > basis. Here, you entirely rely on the firmware to discover whether the
> > CPU needs mitigation or not. You then need to check for a return value
> > of 1, which indicates that although the mitigation is implemented, it is
> > not required on this particular CPU.
> > 
> > But that's probably moot if you don't support BL systems.
> > 
> > > +			harden_branch_predictor = call_hvc_arch_workaround_1;
> > > +			processor.switch_mm = cpu_v7_hvc_switch_mm;
> > > +			spectre_v2_method = "hypervisor";
> > > +			break;
> > > +
> > > +		case PSCI_CONDUIT_SMC:
> > > +			arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
> > > +					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);
> > > +			if ((int)res.a0 < 0)
> > > +				break;
> > > +			harden_branch_predictor = call_smc_arch_workaround_1;
> > > +			processor.switch_mm = cpu_v7_smc_switch_mm;
> > > +			spectre_v2_method = "firmware PSCI";
> > 
> > My previous remark still stands: this is not really PSCI.
> 
> Sorry, no.  Your comment was for the HVC call, not the SMC.  You said
> nothing about this one.

My bad then. For all intents and purposes, they are the same thing,
just serviced by a different exception level.

	M.

-- 
Jazz is not dead, it just smell funny.

  reply	other threads:[~2018-05-23  7:25 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-21 11:42 [PATCH v2 00/14] ARM Spectre variant 2 fixes Russell King - ARM Linux
2018-05-21 11:44 ` [PATCH 01/14] ARM: add CPU part numbers for Cortex A73, A75 and Brahma B15 Russell King
2018-05-21 11:44 ` [PATCH 02/14] ARM: bugs: prepare processor bug infrastructure Russell King
2018-05-21 11:44 ` [PATCH 03/14] ARM: bugs: hook processor bug checking into SMP and suspend paths Russell King
2018-05-24 23:30   ` Florian Fainelli
2018-05-25 10:03     ` Russell King - ARM Linux
2018-05-25 11:31       ` Russell King - ARM Linux
2018-05-21 11:44 ` [PATCH 04/14] ARM: bugs: add support for per-processor bug checking Russell King
2018-05-21 11:44 ` [PATCH 05/14] ARM: spectre: add Kconfig symbol for CPUs vulnerable to Spectre Russell King
2018-05-21 11:44 ` [PATCH 06/14] ARM: spectre-v2: harden branch predictor on context switches Russell King
2018-05-22  3:21   ` Florian Fainelli
2018-05-22  9:55     ` Russell King - ARM Linux
2018-05-22 18:27   ` Tony Lindgren
2018-05-21 11:44 ` [PATCH 07/14] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit Russell King
2018-05-22 18:28   ` Tony Lindgren
2018-05-21 11:45 ` [PATCH 08/14] ARM: spectre-v2: harden user aborts in kernel space Russell King
2018-05-22 17:15   ` Marc Zyngier
2018-05-22 17:56     ` Russell King - ARM Linux
2018-05-22 18:12       ` Russell King - ARM Linux
2018-05-22 18:19         ` Florian Fainelli
2018-05-22 23:25     ` Russell King - ARM Linux
2018-05-21 11:45 ` [PATCH 09/14] ARM: spectre-v2: add PSCI based hardening Russell King
2018-05-22 17:24   ` Marc Zyngier
2018-05-22 17:57     ` Russell King - ARM Linux
2018-05-23  7:25       ` Marc Zyngier [this message]
2018-05-23 19:45     ` Russell King - ARM Linux
2018-05-24 12:03       ` Marc Zyngier
2018-05-24 12:30         ` Russell King - ARM Linux
2018-05-24 12:49           ` Marc Zyngier
2018-05-24 13:04             ` Russell King - ARM Linux
2018-05-21 11:45 ` [PATCH 10/14] ARM: KVM: invalidate BTB on guest exit for Cortex-A12/A17 Russell King
2018-05-21 11:45 ` [PATCH 11/14] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Russell King
2018-05-21 11:45 ` [PATCH 12/14] ARM: spectre-v2: KVM: invalidate icache on guest exit for Brahma B15 Russell King
2018-05-22  3:22   ` Florian Fainelli
2018-05-21 11:45 ` [PATCH 13/14] ARM: KVM: Add SMCCC_ARCH_WORKAROUND_1 fast handling Russell King
2018-05-23 10:50   ` Marc Zyngier
2018-05-21 11:45 ` [PATCH 14/14] ARM: KVM: report support for SMCCC_ARCH_WORKAROUND_1 Russell King
2018-05-24 23:18 ` [PATCH v2 00/14] ARM Spectre variant 2 fixes Florian Fainelli
2018-05-25 10:00   ` Russell King - ARM Linux
  -- strict thread matches above, loose matches on Subject: below --
2018-05-16 10:59 [PATCH 0/14] " Russell King - ARM Linux
2018-05-16 11:01 ` [PATCH 09/14] ARM: spectre-v2: add PSCI based hardening Russell King
2018-05-16 17:01   ` Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=86efi2bzpw.wl-marc.zyngier@arm.com \
    --to=marc.zyngier@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).