Re: [PATCH v3 2/5] KVM: arm64: nvhe: Synchronise with page table walker on TLBI

[Marc Zyngier <maz@kernel.org>]

On Thu, 13 Apr 2023 16:53:04 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> On Thu, Apr 13, 2023 at 09:14:38AM +0100, Marc Zyngier wrote:
> > A TLBI from EL2 impacting EL1 involves messing with the EL1&0
> > translation regime, and the page table walker may still be
> > performing speculative walks.
> > 
> > Piggyback on the existing DSBs to always have a DSB ISH that
> > will synchronise all load/store operations that the PTW may
> > still have.
> > 
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> 
> Reviewed-by: Oliver Upton <oliver.upton@linux.dev>

Thanks!

> 
> > ---
> >  arch/arm64/kvm/hyp/nvhe/tlb.c | 38 ++++++++++++++++++++++++++---------
> >  1 file changed, 29 insertions(+), 9 deletions(-)
> > 
> > diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c
> > index d296d617f589..1da2fc35f94e 100644
> > --- a/arch/arm64/kvm/hyp/nvhe/tlb.c
> > +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c
> > @@ -15,8 +15,31 @@ struct tlb_inv_context {
> >  };
> >  
> >  static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu,
> > -				  struct tlb_inv_context *cxt)
> > +				  struct tlb_inv_context *cxt,
> > +				  bool nsh)
> >  {
> > +	/*
> > +	 * We have two requirements:
> > +	 *
> > +	 * - ensure that the page table updates are visible to all
> > +         *   CPUs, for which a dsb(DOMAIN-st) is what we need, DOMAIN
> > +         *   being either ish or nsh, depending on the invalidation
> > +         *   type.
> > +	 *
> > +	 * - complete any speculative page table walk started before
> > +         *   we trapped to EL2 so that we can mess with the MM
> > +         *   registers out of context, for which dsb(nsh) is enough
> 
> Looks like a few of these lines are indented with spaces, not tabs. Mind
> fixing this when you apply the patches?

Ah, well spotted. Now fixed.

Cheers,

	M.

-- 
Without deviation from the norm, progress is not possible.

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