From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75F7AFED9EC for ; Tue, 17 Mar 2026 16:42:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=h1Gl3h06MBYbFCi+9pRzXmR1yuzigk1EQubRVyAzMng=; b=j1gsXSxZrtqkgmlVzwDjO1HDOL iaEn35rzn6lIIVUU++POm3+0Qs5uEJmMe+bPhxgAbkEJw7Mxytm9MPn3+L/+PgsvNTsCduX+JwvJB JzhW6r7AP0rOhgOaUl7HVRgO0L/yW2w/wPXDn0/TCum23G+VC3J5XtfkFgLLTR0bRSL6ZAIsB5E3T VLJttzIuqUUSmzRDt0whz+yTf00MIocTISVRP+INmmLx4EzOTp/BqBwgtsWQG+aaXlDwLM6BY+fhv P0eZ5GKYZXuwLsA/I2b69CGgqqw70l7R2BQYsdjX7xj/N0BHkG03KJhDvM9mMcyxY2ltEeA3pJ/ST bWTnuwgw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w2XV8-00000006r2H-3sGW; Tue, 17 Mar 2026 16:42:38 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1w2XV6-00000006r1e-0TPS for linux-arm-kernel@lists.infradead.org; Tue, 17 Mar 2026 16:42:37 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 6159A4046C; Tue, 17 Mar 2026 16:42:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BEAEC2BC86; Tue, 17 Mar 2026 16:42:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773765755; bh=4x+SUB7RnGfi/LSfJmoWTDH7Eoq0uMpUCleOwVf4ExU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OfwIua9QstMlgDUMV8+XypkhDNNX48tVir7FIyfdUMeU23jSrFEEEJ6KezQothxip HcVyLUcIUGSzYToEALLvdeLp7T1yMIhjEzaUlDX1zYgpriAV+KJM7/wwbOdYwOfrjd 8NYeGd/hy15GQs0qwaYy+ocfxrXFK9LdiDJ+Q7Wr7JFdq6NVfBjK668PabhGbxh8Az tnKGfHwRmh7QKwIj4qBrkOqfEBtA+hnkIu+FVcCQV1IjdhU7RLv8zF3+NzecTxG6vT CGs36hi3T7PsvhAmwYBDKrp/X/hk7os6mKOybBXyU0v3K6LV1QMp/JR5To93yLv4vD Vf1bPtEPm0a1w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w2XV3-00000002vtQ-01ZR; Tue, 17 Mar 2026 16:42:33 +0000 Date: Tue, 17 Mar 2026 16:42:32 +0000 Message-ID: <86h5qe5rwn.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v6 20/39] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 In-Reply-To: <20260317113949.2548118-21-sascha.bischoff@arm.com> References: <20260317113949.2548118-1-sascha.bischoff@arm.com> <20260317113949.2548118-21-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260317_094236_191067_79100C7E X-CRM114-Status: GOOD ( 24.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 17 Mar 2026 11:45:10 +0000, Sascha Bischoff wrote: > > Initialise the private interrupts (PPIs, only) for GICv5. This means > that a GICv5-style intid is generated (which encodes the PPI type in > the top bits) instead of the 0-based index that is used for older > GICs. > > Additionally, set all of the GICv5 PPIs to use Level for the handling > mode, with the exception of the SW_PPI which uses Edge. This matches > the architecturally-defined set in the GICv5 specification (the CTIIRQ > handling mode is IMPDEF, so Level has been picked for that). > > Signed-off-by: Sascha Bischoff > Reviewed-by: Jonathan Cameron > --- > arch/arm64/kvm/vgic/vgic-init.c | 95 +++++++++++++++++++++++---------- > 1 file changed, 66 insertions(+), 29 deletions(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c > index e1be9c5ada7b3..f8d7d5a895e79 100644 > --- a/arch/arm64/kvm/vgic/vgic-init.c > +++ b/arch/arm64/kvm/vgic/vgic-init.c > @@ -250,9 +250,64 @@ int kvm_vgic_vcpu_nv_init(struct kvm_vcpu *vcpu) > return ret; > } > > +static void vgic_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type) > +{ > + struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i]; > + > + INIT_LIST_HEAD(&irq->ap_list); > + raw_spin_lock_init(&irq->irq_lock); > + irq->vcpu = NULL; > + irq->target_vcpu = vcpu; > + refcount_set(&irq->refcount, 0); > + > + irq->intid = i; > + if (vgic_irq_is_sgi(i)) { > + /* SGIs */ > + irq->enabled = 1; > + irq->config = VGIC_CONFIG_EDGE; > + } else { > + /* PPIs */ > + irq->config = VGIC_CONFIG_LEVEL; > + } > + > + switch (type) { > + case KVM_DEV_TYPE_ARM_VGIC_V3: > + irq->group = 1; > + irq->mpidr = kvm_vcpu_get_mpidr_aff(vcpu); > + break; > + case KVM_DEV_TYPE_ARM_VGIC_V2: > + irq->group = 0; > + irq->targets = BIT(vcpu->vcpu_id); > + break; > + } > +} > + > +static void vgic_v5_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type) > +{ > + struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i]; > + > + INIT_LIST_HEAD(&irq->ap_list); > + raw_spin_lock_init(&irq->irq_lock); > + irq->vcpu = NULL; > + irq->target_vcpu = vcpu; > + refcount_set(&irq->refcount, 0); > + > + irq->intid = vgic_v5_make_ppi(i); > + > + /* The only Edge architected PPI is the SW_PPI */ > + if (i == GICV5_ARCH_PPI_SW_PPI) > + irq->config = VGIC_CONFIG_EDGE; > + else > + irq->config = VGIC_CONFIG_LEVEL; > + > + /* Register the GICv5-specific PPI ops */ > + vgic_v5_set_ppi_ops(irq); I'd definitely expect this to use the generic accessor instead of something v5-specific. Thanks, M. -- Without deviation from the norm, progress is not possible.