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Fri, 02 Aug 2024 10:29:36 +0100 Date: Fri, 02 Aug 2024 10:29:36 +0100 Message-ID: <86h6c31ddr.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com Subject: Re: [BOOT-WRAPPER 03/11] aarch64: Implement cpu_init_arch() In-Reply-To: <20240729161501.1806271-4-mark.rutland@arm.com> References: <20240729161501.1806271-1-mark.rutland@arm.com> <20240729161501.1806271-4-mark.rutland@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.3 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_022942_239043_786DE2EA X-CRM114-Status: GOOD ( 24.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 29 Jul 2024 17:14:53 +0100, Mark Rutland wrote: > > When the boot-wrapper is entered at EL2 it does not initialise > CNTFRQ_EL0, and in future it may need to initialize other CPU state > regardless of the exeption level it was entered at. > > Use a common cpu_init_arch() function to initialize CPU state regardless > of the exception level the boot-wrapper was entered at. > > Signed-off-by: Mark Rutland > Cc: Akos Denke > Cc: Andre Przywara > Cc: Luca Fancellu > Cc: Marc Zyngier > --- > arch/aarch64/boot.S | 4 +++- > arch/aarch64/init.c | 12 +++++++++--- > 2 files changed, 12 insertions(+), 4 deletions(-) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 51ef41b..d8d38dd 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -51,7 +51,7 @@ reset_at_el3: > > bl cpu_init_bootwrapper > > - bl cpu_init_el3 > + bl cpu_init_arch > > bl gic_secure_init > > @@ -82,6 +82,8 @@ reset_at_el2: > > bl cpu_init_bootwrapper > > + bl cpu_init_arch > + > b start_bootmethod > > err_invalid_id: > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index c9fc7f1..49abdf7 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -52,7 +52,7 @@ static inline bool cpu_has_permission_indirection(void) > return mrs(ID_AA64MMFR3_EL1) & mask; > } > > -void cpu_init_el3(void) > +static void cpu_init_el3(void) > { > unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE; > unsigned long mdcr = 0; > @@ -153,8 +153,6 @@ void cpu_init_el3(void) > > msr(SMCR_EL3, smcr); > } > - > - msr(CNTFRQ_EL0, COUNTER_FREQ); > } > > #ifdef PSCI > @@ -171,3 +169,11 @@ bool cpu_init_psci_arch(void) > return true; > } > #endif > + > +void cpu_init_arch(void) > +{ > + if (mrs(CurrentEL) == CURRENTEL_EL3) > + cpu_init_el3(); > + > + msr(CNTFRQ_EL0, COUNTER_FREQ); > +} Hmmm. This means that you cannot use the BW on a system where EL3 is implemented, but where you decide to enter at EL2 anyway (the write to CNTFRQ_EL0 will UNDEF). I don't care much (I always want the BW to be the first piece of SW to run), but this is a rather subtle change in behaviour, and we'd better capture it in the commit message. With that, Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.