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Thu, 29 Oct 2026 17:05:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793293511; bh=LVRxZ24pqtgoa//AHQI5Xv+cMRAGXk2uxfsL1IU6GrI=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=G0ykgAeC8Jlr/lcfDgv58kfm/oA5Cqf1X+4jYhIrQD3Kou6DYng9U8chgQ0LB3y5M Yt7cvZBcvOTLO86KBx8YRxUQErNyGF0JFHkOhjzzg5M8+mpey1kQIt0dS07g+9d6HZ 9RepnMfzjxY29/6VHS+wjqy16gp0NNHNg5GeYApljtXKHzbPP+0kpCxrhJhLYjpV/2 uWNecWqCg1+1CE1RslIgmixd81EXgnXQfnR0mLvdEbU8+Q747HGhFQyEVytR/uxWLR lvjRAxnZlIM5nhArfjEsGxc1XdqRH1n4nA9aQjFBGYgPl08Sky82QepCv814D8njvW wI4JfCiXXKpCQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1xMTYr-00000008dbp-06u5; Thu, 29 Oct 2026 17:05:09 +0000 Date: Thu, 29 Oct 2026 17:05:08 +0000 Message-ID: <86ik2kxwsb.wl-maz@kernel.org> From: Marc Zyngier To: francesco.boccola@unina.it Cc: Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC v2] KVM: arm64: nVHE: Flush all TLBs when freeing a VM's stage-2 In-Reply-To: <20261029-nvhe-stage2-flush-v2-1-096723b28bef@unina.it> References: <20261029-nvhe-stage2-flush-v2-1-096723b28bef@unina.it> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Archived-By: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: francesco.boccola@unina.it, oupton@kernel.org, fuad.tabba@linux.dev, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, 29 Oct 2026 15:34:48 +0000, Francesco Boccola via B4 Relay wrote: > > From: Francesco Boccola > > kvm_free_stage2_pgd() frees a VM's stage-2 page tables without invalidating > the TLBs. That is correct: the VM's VMID is not reused before the next VMID > rollover, and flush_context() then invalidates the entries of all VMIDs on > all CPUs (TLBI ALLE1IS). > > In nVHE mode, however, a CPU that ran a guest makes the host's broadcast > TLB invalidations more expensive for the whole system until then, which > with 16-bit VMIDs usually means until the host reboots. Does it? Why? What permanent state is kept in the CPU TLBs that makes invalidation slower? > With stress-ng > --tlb-shootdown on three CPUs of a cluster, the cyclictest maximum on a > fourth, isolated CPU goes, before and after one guest: > - Cortex-A53 (Zynq UltraScale+ KV260, no VHE, 6.1.70-rt): 53-72 us -> > 83-164 us; > - Cortex-A55 (RK3588, kvm-arm.mode=nvhe, kvmarm/next): 18-23 -> 78-97 us; > - Cortex-A76 (RK3588, kvm-arm.mode=nvhe, kvmarm/next): 16-30 -> 74-80 us. > It crosses clusters: after a guest on an A55, an isolated A76 goes from > 14-18 us to 129-154 us. The same happens on kernel 6.12.113 (20-24 -> 44-49 > us on the A55) and on 7.1.9 with and without PREEMPT_RT. > > One guest that turns its stage-1 MMU on, even for a few microseconds, is > enough; a guest that keeps its MMU off is not. With VHE nothing changes. > > The state is in the CPU that ran the guest: a local TLBI ALLE1 on that CPU > at teardown removes the effect on every CPU, the same on all the other CPUs I note that the hack you are adding in this patch is a broadcast TLBI, not a local one. > does not. Invalidating the dead VM's VMID (TLBI VMALLS12E1IS, as pKVM does > at teardown) does not remove it either, whether stage 2 is disabled while > it is issued (as __kvm_tlb_flush_vmid() does from the host's context) or > enabled; nor does invalidating VMID 0 or the host's stage 1 (A53). VMID 0 is not special. This is just a convention, and you could use VMID $(RANDOM) as long as you use it consistently everywhere. > > So do the rollover's invalidation when the stage 2 of a VM that has run is > freed, in nVHE mode. That costs one TLB refill on every CPU per VM > teardown; 500 VMs created, run and torn down one after the other take 32.1 > ms each with it and 33.4 ms without, and an isolated CPU meanwhile sees no > change in latency (15 us against 13 us). Not a lot in this report makes sense, I'm afraid. I'm not pretending that what you are seeing isn't real (I haven't tried it), but without a actual description of what the root cause of the problem is, we're not going to randomly sprinkle TLB invalidations that are not architecturally required. M. -- Without deviation from the norm, progress is not possible.