[PATCH] arm64/sysreg: Correct the values for GICv4.1

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* [PATCH] arm64/sysreg: Correct the values for GICv4.1
@ 2024-07-18 21:55 Raghavendra Rao Ananta
  2024-07-19  7:55 ` Marc Zyngier
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Raghavendra Rao Ananta @ 2024-07-18 21:55 UTC (permalink / raw)
  To: Oliver Upton, Marc Zyngier, Catalin Marinas, Will Deacon,
	Mark Brown
  Cc: Raghavendra Rao Anata, linux-arm-kernel, kvmarm, linux-kernel,
	kvm

Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
Hence, correct them to reflect ARM ARM.

Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
 arch/arm64/tools/sysreg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a4c1dd4741a47..7ceaa1e0b4bc2 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -149,7 +149,7 @@ Res0	63:32
 UnsignedEnum	31:28	GIC
 	0b0000	NI
 	0b0001	GICv3
-	0b0010	GICv4p1
+	0b0011	GICv4p1
 EndEnum
 UnsignedEnum	27:24	Virt_frac
 	0b0000	NI
@@ -903,7 +903,7 @@ EndEnum
 UnsignedEnum	27:24	GIC
 	0b0000	NI
 	0b0001	IMP
-	0b0010	V4P1
+	0b0011	V4P1
 EndEnum
 SignedEnum	23:20	AdvSIMD
 	0b0000	IMP

base-commit: 0c3836482481200ead7b416ca80c68a29cfdaabd
-- 
2.45.2.1089.g2a221341d9-goog



^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
  2024-07-18 21:55 [PATCH] arm64/sysreg: Correct the values for GICv4.1 Raghavendra Rao Ananta
@ 2024-07-19  7:55 ` Marc Zyngier
  2024-07-22  8:00   ` Anshuman Khandual
  2024-07-21  9:29 ` Zenghui Yu
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 7+ messages in thread
From: Marc Zyngier @ 2024-07-19  7:55 UTC (permalink / raw)
  To: Raghavendra Rao Ananta
  Cc: Oliver Upton, Catalin Marinas, Will Deacon, Mark Brown,
	linux-arm-kernel, kvmarm, linux-kernel, kvm

On Thu, 18 Jul 2024 22:55:32 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
> 
> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
> Hence, correct them to reflect ARM ARM.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> ---
>  arch/arm64/tools/sysreg | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index a4c1dd4741a47..7ceaa1e0b4bc2 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -149,7 +149,7 @@ Res0	63:32
>  UnsignedEnum	31:28	GIC
>  	0b0000	NI
>  	0b0001	GICv3
> -	0b0010	GICv4p1
> +	0b0011	GICv4p1
>  EndEnum
>  UnsignedEnum	27:24	Virt_frac
>  	0b0000	NI
> @@ -903,7 +903,7 @@ EndEnum
>  UnsignedEnum	27:24	GIC
>  	0b0000	NI
>  	0b0001	IMP
> -	0b0010	V4P1
> +	0b0011	V4P1

I wonder why we have different naming schemes for the same feature...

>  EndEnum
>  SignedEnum	23:20	AdvSIMD
>  	0b0000	IMP
> 

Yup, this looks correct and checks out against revision H.b of the GICv3
spec, revision K.a of the ARM ARM, and even I.a (which the original
patches were referencing).

Once more, it shows that these dumps should be automatically generated
from the XML instead of (creatively) hand-written.

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
  2024-07-19  7:55 ` Marc Zyngier
@ 2024-07-22  8:00   ` Anshuman Khandual
  0 siblings, 0 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-07-22  8:00 UTC (permalink / raw)
  To: Marc Zyngier, Raghavendra Rao Ananta
  Cc: Oliver Upton, Catalin Marinas, Will Deacon, Mark Brown,
	linux-arm-kernel, kvmarm, linux-kernel, kvm



On 7/19/24 13:25, Marc Zyngier wrote:
> On Thu, 18 Jul 2024 22:55:32 +0100,
> Raghavendra Rao Ananta <rananta@google.com> wrote:
>>
>> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
>> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
>> Hence, correct them to reflect ARM ARM.
>>
>> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
>> ---
>>  arch/arm64/tools/sysreg | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index a4c1dd4741a47..7ceaa1e0b4bc2 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -149,7 +149,7 @@ Res0	63:32
>>  UnsignedEnum	31:28	GIC
>>  	0b0000	NI
>>  	0b0001	GICv3
>> -	0b0010	GICv4p1
>> +	0b0011	GICv4p1
>>  EndEnum
>>  UnsignedEnum	27:24	Virt_frac
>>  	0b0000	NI
>> @@ -903,7 +903,7 @@ EndEnum
>>  UnsignedEnum	27:24	GIC
>>  	0b0000	NI
>>  	0b0001	IMP
>> -	0b0010	V4P1
>> +	0b0011	V4P1
> 
> I wonder why we have different naming schemes for the same feature...

Both definitions were added via different commits and different developers who
might just have interpreted the following common description bit differently.

"System register interface to version 4.1 of the GIC CPU interface is supported"

1224308075f1 ("arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation")
cea08f2bf406 ("arm64/sysreg: Convert ID_AA64PFR0_EL1 to automatic generation")

But I agree that same fields should be named exactly the same both in their 32
bit and 64 bit variants.

> 
>>  EndEnum
>>  SignedEnum	23:20	AdvSIMD
>>  	0b0000	IMP
>>
> 
> Yup, this looks correct and checks out against revision H.b of the GICv3
> spec, revision K.a of the ARM ARM, and even I.a (which the original
> patches were referencing).
> 
> Once more, it shows that these dumps should be automatically generated
> from the XML instead of (creatively) hand-written.
> 
> Reviewed-by: Marc Zyngier <maz@kernel.org>
> 
> 	M.
> 


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
  2024-07-18 21:55 [PATCH] arm64/sysreg: Correct the values for GICv4.1 Raghavendra Rao Ananta
  2024-07-19  7:55 ` Marc Zyngier
@ 2024-07-21  9:29 ` Zenghui Yu
  2024-07-22  8:37   ` Anshuman Khandual
  2024-07-22  8:39 ` Anshuman Khandual
  2024-07-23 15:46 ` Will Deacon
  3 siblings, 1 reply; 7+ messages in thread
From: Zenghui Yu @ 2024-07-21  9:29 UTC (permalink / raw)
  To: Raghavendra Rao Ananta
  Cc: Oliver Upton, Marc Zyngier, Catalin Marinas, Will Deacon,
	Mark Brown, linux-arm-kernel, kvmarm, linux-kernel, kvm

On 2024/7/19 5:55, Raghavendra Rao Ananta wrote:
> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
> Hence, correct them to reflect ARM ARM.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> ---
>  arch/arm64/tools/sysreg | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index a4c1dd4741a47..7ceaa1e0b4bc2 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -149,7 +149,7 @@ Res0	63:32
>  UnsignedEnum	31:28	GIC
>  	0b0000	NI
>  	0b0001	GICv3
> -	0b0010	GICv4p1
> +	0b0011	GICv4p1
>  EndEnum
>  UnsignedEnum	27:24	Virt_frac
>  	0b0000	NI
> @@ -903,7 +903,7 @@ EndEnum
>  UnsignedEnum	27:24	GIC
>  	0b0000	NI
>  	0b0001	IMP
> -	0b0010	V4P1
> +	0b0011	V4P1
>  EndEnum
>  SignedEnum	23:20	AdvSIMD
>  	0b0000	IMP

Fortunately there is no user for this bit inside kernel. We had checked
against the correct hard-coded value (0x3) in gic_cpuif_has_vsgi().

Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
  2024-07-21  9:29 ` Zenghui Yu
@ 2024-07-22  8:37   ` Anshuman Khandual
  0 siblings, 0 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-07-22  8:37 UTC (permalink / raw)
  To: Zenghui Yu, Raghavendra Rao Ananta
  Cc: Oliver Upton, Marc Zyngier, Catalin Marinas, Will Deacon,
	Mark Brown, linux-arm-kernel, kvmarm, linux-kernel, kvm



On 7/21/24 14:59, Zenghui Yu wrote:
> On 2024/7/19 5:55, Raghavendra Rao Ananta wrote:
>> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
>> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
>> Hence, correct them to reflect ARM ARM.
>>
>> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
>> ---
>>  arch/arm64/tools/sysreg | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
>> index a4c1dd4741a47..7ceaa1e0b4bc2 100644
>> --- a/arch/arm64/tools/sysreg
>> +++ b/arch/arm64/tools/sysreg
>> @@ -149,7 +149,7 @@ Res0    63:32
>>  UnsignedEnum    31:28    GIC
>>      0b0000    NI
>>      0b0001    GICv3
>> -    0b0010    GICv4p1
>> +    0b0011    GICv4p1
>>  EndEnum
>>  UnsignedEnum    27:24    Virt_frac
>>      0b0000    NI
>> @@ -903,7 +903,7 @@ EndEnum
>>  UnsignedEnum    27:24    GIC
>>      0b0000    NI
>>      0b0001    IMP
>> -    0b0010    V4P1
>> +    0b0011    V4P1
>>  EndEnum
>>  SignedEnum    23:20    AdvSIMD
>>      0b0000    IMP
> 
> Fortunately there is no user for this bit inside kernel. We had checked
> against the correct hard-coded value (0x3) in gic_cpuif_has_vsgi().

which probably helped this problem to be left unnoticed till now :) but I
guess it would be better to use ID_AA64PFR0_EL1_GIC_V4P1 there instead.

> 
> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
> 


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
  2024-07-18 21:55 [PATCH] arm64/sysreg: Correct the values for GICv4.1 Raghavendra Rao Ananta
  2024-07-19  7:55 ` Marc Zyngier
  2024-07-21  9:29 ` Zenghui Yu
@ 2024-07-22  8:39 ` Anshuman Khandual
  2024-07-23 15:46 ` Will Deacon
  3 siblings, 0 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-07-22  8:39 UTC (permalink / raw)
  To: Raghavendra Rao Ananta, Oliver Upton, Marc Zyngier,
	Catalin Marinas, Will Deacon, Mark Brown
  Cc: linux-arm-kernel, kvmarm, linux-kernel, kvm



On 7/19/24 03:25, Raghavendra Rao Ananta wrote:
> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
> Hence, correct them to reflect ARM ARM.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> ---
>  arch/arm64/tools/sysreg | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index a4c1dd4741a47..7ceaa1e0b4bc2 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -149,7 +149,7 @@ Res0	63:32
>  UnsignedEnum	31:28	GIC
>  	0b0000	NI
>  	0b0001	GICv3
> -	0b0010	GICv4p1
> +	0b0011	GICv4p1
>  EndEnum
>  UnsignedEnum	27:24	Virt_frac
>  	0b0000	NI
> @@ -903,7 +903,7 @@ EndEnum
>  UnsignedEnum	27:24	GIC
>  	0b0000	NI
>  	0b0001	IMP
> -	0b0010	V4P1
> +	0b0011	V4P1
>  EndEnum
>  SignedEnum	23:20	AdvSIMD
>  	0b0000	IMP
> 
> base-commit: 0c3836482481200ead7b416ca80c68a29cfdaabd

This checks against ARM DDI 0487K.a and ddi0601/2024-06 XML.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
  2024-07-18 21:55 [PATCH] arm64/sysreg: Correct the values for GICv4.1 Raghavendra Rao Ananta
                   ` (2 preceding siblings ...)
  2024-07-22  8:39 ` Anshuman Khandual
@ 2024-07-23 15:46 ` Will Deacon
  3 siblings, 0 replies; 7+ messages in thread
From: Will Deacon @ 2024-07-23 15:46 UTC (permalink / raw)
  To: Oliver Upton, Marc Zyngier, Catalin Marinas, Mark Brown,
	Raghavendra Rao Ananta
  Cc: kernel-team, Will Deacon, linux-arm-kernel, kvmarm, linux-kernel,
	kvm

On Thu, 18 Jul 2024 21:55:32 +0000, Raghavendra Rao Ananta wrote:
> Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
> ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
> Hence, correct them to reflect ARM ARM.
> 
> 

Applied to arm64 (for-next/core), thanks!

[1/1] arm64/sysreg: Correct the values for GICv4.1
      https://git.kernel.org/arm64/c/f3dfcd25455b

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2024-07-23 15:48 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-18 21:55 [PATCH] arm64/sysreg: Correct the values for GICv4.1 Raghavendra Rao Ananta
2024-07-19  7:55 ` Marc Zyngier
2024-07-22  8:00   ` Anshuman Khandual
2024-07-21  9:29 ` Zenghui Yu
2024-07-22  8:37   ` Anshuman Khandual
2024-07-22  8:39 ` Anshuman Khandual
2024-07-23 15:46 ` Will Deacon

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