From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01A6EC77B7D for ; Mon, 15 May 2023 13:42:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ywsnwqx1F0J+6Hl9GDEK+k14ntrF0+rrFUS5E/643bM=; b=mDC/+gD/oPVZTq N0WtR7wxHc7mqom9/nmE3Zsgik1aWkojWQT50O56nCE6WJ0BaZnD8jIauynVTxB6ZXUtTxsNUMLdu HJAxA0cvP3dbuR6gyffO2jzzYjrsgikAiO/bkDaydQ6FbGRRkazcSxt7tiBa+AfCCnPlUvWwp5h1T tI0v3KlSw71tmcN+n8gToMPK0oNWpwup1vGfRxWlGjTNnfCp4ElimPMLdgu2haXaHMhFRv4YqGnOu 3Yp3jiG132ZzJEDlY0TvS2MhEimGHYYHnogpLywUJZJpHg4AHcBMiedb4R7ynaleppMwtJCEtcos6 SZDNZR6losEHYcJ9tJFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pyYSu-002I5u-1x; Mon, 15 May 2023 13:42:16 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pyYSr-002I4k-1N for linux-arm-kernel@lists.infradead.org; Mon, 15 May 2023 13:42:15 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 30E716205E; Mon, 15 May 2023 13:42:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B237C433EF; Mon, 15 May 2023 13:42:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684158131; bh=M4oE5zTdWt8UHV4GZZzQWHxwvY1pWNA64W1u7qoq6ps=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=TmqSVDExYGsRO2K8Sr504iEbECj7mmXN+tX+jBP/YkiNJyOFVguN1tx/fz/upZnb2 x+kFp89hzh5BTr3BJTqPmsiN+i28yvRIFmOf+Aw3VZ6seA42mRALby3YUM5YSpnIt6 hdLbuG0L1xvPDCNVbF46ocLxq7LPd+GdoaBUKYIf2jEK5bqiLa+9V5UZvv+aA5bWL4 MP6ggou/A/Yq/YfODE7zL5mGm1T3L/cY1lZ9E7R2hlOLehBOm5br3W+QYYIzTg3Gpd DuIsOxiEcmaLfeKhV8Gf4KzNGtaN9hiXkwpxpX101QU5nZlXPTF9/RsIH4tMA5oH9w 3/X0VJbNyJEgw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pyYSm-00FFaJ-W0; Mon, 15 May 2023 14:42:09 +0100 Date: Mon, 15 May 2023 14:42:08 +0100 Message-ID: <86ilctn233.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Brown , linux-kernel@vger.kernel.org Subject: Re: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1 In-Reply-To: <20230515105328.239204-1-anshuman.khandual@arm.com> References: <20230515105328.239204-1-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230515_064213_570782_7AF764D6 X-CRM114-Status: GOOD ( 27.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 15 May 2023 11:53:28 +0100, Anshuman Khandual wrote: > > This disables EL2 traps for BRBE instructions executed in EL1. This would > enable BRBE to be configured and used successfully in the guest kernel. > While here, this updates Documentation/arm64/booting.rst as well. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Brown > Cc: Marc Zyngier > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > This patch applies on v6.4-rc2 > > Changes in V2: > > - Updated Documentation/arm64/booting.rst > > Changes in V1: > > https://lore.kernel.org/all/20230324055127.2228330-1-anshuman.khandual@arm.com/ > > Documentation/arm64/booting.rst | 8 ++++++++ > arch/arm64/include/asm/el2_setup.h | 10 ++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst > index ffeccdd6bdac..cb9e151f6928 100644 > --- a/Documentation/arm64/booting.rst > +++ b/Documentation/arm64/booting.rst > @@ -379,6 +379,14 @@ Before jumping into the kernel, the following conditions must be met: > > - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. > > + For CPUs with the Branch Record Buffer Extension (FEAT_BRBE): > + > + - If the kernel is entered at EL1 and EL2 is present: > + > + - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1. > + > + - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1. > + > The requirements described above for CPU mode, caches, MMUs, architected > timers, coherency and system registers apply to all CPUs. All CPUs must > enter the kernel in the same exception level. Where the values documented > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index 037724b19c5c..06bf321a17be 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -161,6 +161,16 @@ > msr_s SYS_HFGWTR_EL2, x0 > msr_s SYS_HFGITR_EL2, xzr > > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 > + cbz x1, .Lskip_brbe_\@ > + > + mov x0, xzr > + orr x0, x0, #HFGITR_EL2_nBRBIALL > + orr x0, x0, #HFGITR_EL2_nBRBINJ > + msr_s SYS_HFGITR_EL2, x0 This will break badly if someone inserts something between this hunk and the initial setting of HFGITR_EL2. I'd really prefer a RMW approach. It's not that this code has to be optimised anyway. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel