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Mon, 06 Jul 2026 08:44:39 +0000 Date: Mon, 06 Jul 2026 09:44:39 +0100 Message-ID: <86jyr8pkw8.wl-maz@kernel.org> From: Marc Zyngier To: Tangnianyao Cc: Wei-Lin Chang , , , , , , , , , , , "guoyang (C)" , "huanglingyan (A)" , "Wangzhou (B)" Subject: Re: Question about the "TLBs and I-cache are private to each vCPU" guarantee with VTTBR_EL2.CnP In-Reply-To: <21eb51aa-443c-4d08-b4dd-3f813bbc9880@huawei.com> References: <292b5734-9005-6db0-da08-3da04628e620@huawei.com> <86o6gkpokm.wl-maz@kernel.org> <21eb51aa-443c-4d08-b4dd-3f813bbc9880@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tangnianyao@huawei.com, weilin.chang@arm.com, oupton@kernel.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, guoyang2@huawei.com, huanglingyan2@huawei.com, wangzhou1@hisilicon.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 06 Jul 2026 09:25:46 +0100, Tangnianyao wrote: >=20 >=20 >=20 > On 7/6/2026 15:25, Marc Zyngier wrote: > > On Mon, 06 Jul 2026 04:30:30 +0100, > > Tangnianyao wrote: > >> > >> > >> On 7/6/2026 1:28, Wei-Lin Chang wrote: > >>> Hi, > >>> > >>> Let me try to answer this: > >>> > >>> On Sat, Jul 04, 2026 at 03:45:56PM +0800, Tangnianyao wrote: > >>>> Hi, all > >>>> > >>>> I'm trying to understand the TLB and I-cache invalidation in > >>>> `kvm_arch_vcpu_load()` that is intended to "guarantee that both TLBs= and > >>>> I-cache are private to each vCPU". > >>>> > >>>> As I understand it, when `VTTBR_EL2.CnP =3D=3D 1`, `__kvm_flush_cpu_= context()` > >>>> only performs a local TLB and I-cache invalidation, which does not s= eem > >>>> sufficient to guarantee that property. > >>>> > >>>> In fact, even if the invalidation were extended to the Inner Shareab= le > >>>> domain, it still seems difficult to guarantee =E2=80=9CTLBs and I-ca= che are > >>>> private to each vCPU=E2=80=9D, when `VTTBR_EL2.CnP =3D=3D 1`, as lon= g as multiple > >>>> vCPUs from the same VM may be running concurrently on different PEs. > >>> I think you have missed that when 2 stages are involved, both stages > >>> have to set CnP =3D=3D 1 in order to share TLB entries (Arm ARM R_ZVR= ZW). > >>> So if TLB entry sharing happens, the guest kernel must have allowed it > >>> in the first place (by setting TTBR0/1_EL1.CnP =3D=3D 1), hence accid= ental > >>> sharing that you are worried about won't happen. > >>> > >>> __kvm_flush_cpu_context() is solving problems that occur when multiple > >>> vCPUs of a VM are multiplexed on a single physical CPU. > >> Thanks for you answer. > >> > >> If guest kernel allow TLB shared across CPUs by setting TTBR0/1_EL1.Cn= P =3D=3D 1, > >> does kvm still need to guarantee that TLBs are private to each vCPU? > > Yes, because there is nothing that describes which physical CPUs > > actually share TLBs. So the only possible course of action is to > > ignore what the guest says and fallback to something that is safe. > > > >>>> So I have two questions: > >>>> > >>>> 1. What is the rationale behind the comment that "guarantee that bot= h TLBs > >>>> and I-cache are private to each vCPU"? > >>> I assume you are asking why keeping both TLBs and I-cache private per > >>> each vCPU is required. The fundamental answer is that each physical C= PU > >>> is expected to have its own TLB and I-cache, so we must uphold that > >>> property for vCPUs as well. vCPUs can be scheduled on the same physic= al > >>> CPU, and use the same physical TLB/I-cache, obviously, so extra > >>> invalidations need to be done. > >> Let's assume that both Stage-1 CnP and Stage-2 CnP are enabled. > >> > >> As I understand it, the architecture permits TLB to be shared by multi= ple > >> PEs within an Inner Shareable domain. Right? > >> > >> If an implementation allows TLB entries to be shared in this way, it s= eems > >> that the current invalidation performed by kvm would no longer be suff= icient > >> to guarantee that TLBs are private to each vCPU. > > Care to explain why? > > > > The core assumption is that a TLBI take effect on all the PEs the TLB > > is shared with. If this doesn't work, then CnP is unusable, because it > > is then impossible to guarantee that a translation will be refetched > > (you could always hit in another PEs TLBs). Such an implementation > > would be terminally broken. > > > > M. > > > For example: > Sharing the TLB between the two SMT threads of the same physical core can > reduce hardware cost while increasing the effective TLB coverage. I have a precise idea of what TLB sharing can achieve. > A local TLBI take effect on the whole TLB shared by the two SMT threads, > with the sharing enabled by CnP. >=20 > In this scenario, enabling CnP in KVM appears to break the guarantee that > TLBs are private to each vCPU when multiple vCPUs of the same VM run > concurrently on different SMT threads of the same PE. Please stop inventing your own terminology. A PE *is* a thread in the architecture. There is no such thing as "threads of the same PE". But more to the point: if TLBI invalidates the relevant TLBs for all the PEs that share them, *why* isn't the current KVM behaviour not enough to ensure that the vcpu will not hit old TLBs that are there as a result of a vcpu having run there previously? Please explain. M. --=20 Without deviation from the norm, progress is not possible.