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Sun, 24 Nov 2024 12:38:34 +0000 Date: Sun, 24 Nov 2024 12:38:33 +0000 Message-ID: <86jzcsvmba.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, james.clark@linaro.org, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, broonie@kernel.org, qperret@google.com Subject: Re: [PATCH v2 07/12] KVM: arm64: Rework specifying restricted features for protected VMs In-Reply-To: <20241122110622.3010118-8-tabba@google.com> References: <20241122110622.3010118-1-tabba@google.com> <20241122110622.3010118-8-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, james.clark@linaro.org, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, broonie@kernel.org, qperret@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241124_043838_598972_6B8B896B X-CRM114-Status: GOOD ( 22.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 22 Nov 2024 11:06:17 +0000, Fuad Tabba wrote: > > The existing code didn't properly distinguish between signed and > unsigned features, and was difficult to read and to maintain. > Rework it using the same method used in other parts of KVM when > handling vcpu features. > > Signed-off-by: Fuad Tabba > --- > .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 1 - > arch/arm64/kvm/hyp/nvhe/sys_regs.c | 356 +++++++++--------- > 2 files changed, 186 insertions(+), 171 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > index 69e26d1a0ebe..37a6d2434e47 100644 > --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > @@ -198,7 +198,6 @@ > FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3), ID_AA64ISAR2_EL1_APA3_PAuth) \ > ) > > -u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); > bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code); > bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code); > void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu); > diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c > index 3aa76b018f70..cea3b099dc56 100644 > --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c > +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c > @@ -28,221 +28,237 @@ u64 id_aa64mmfr1_el1_sys_val; > u64 id_aa64mmfr2_el1_sys_val; > u64 id_aa64smfr0_el1_sys_val; > > -/* > - * Inject an unknown/undefined exception to an AArch64 guest while most of its > - * sysregs are live. > - */ > -static void inject_undef64(struct kvm_vcpu *vcpu) > -{ > - u64 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT); > - > - *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR); > - *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR); > - > - kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC); > - > - __kvm_adjust_pc(vcpu); > - > - write_sysreg_el1(esr, SYS_ESR); > - write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); > - write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR); > - write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR); > -} > +struct pvm_feature { > + int shift; > + int width; > + u64 mask; > + u64 max_supported; > + bool is_signed; Most of this is very similar to struct arm64_ftr_bits. Can you align the types and names with it? And do you really need 'mask', which can be derived from shift and width? max_supported as an unsigned value is also potentially troublesome for signed features. And does it need to be 64bit wide? > + bool (*vcpu_supported)(const struct kvm_vcpu *vcpu); We really need to find a way to kill this. The two features that stick out badly are SVE and PAuth, and I don't see why we can't eventually track them at the VM level instead (despite the userspace API). Thanks, M. -- Without deviation from the norm, progress is not possible.