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Fri, 23 Jan 2026 13:21:24 +0000 Date: Fri, 23 Jan 2026 13:21:24 +0000 Message-ID: <86ldhobh2j.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Quentin Perret , Fuad Tabba Subject: Re: [PATCH 3/6] KVM: arm64: Make stage2_pte_cacheable() return false when S2_AS_S1 is set In-Reply-To: References: <20260119105651.255693-1-maz@kernel.org> <20260119105651.255693-4-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, qperret@google.com, tabba@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 22 Jan 2026 15:04:17 +0000, Will Deacon wrote: > > On Mon, Jan 19, 2026 at 10:56:48AM +0000, Marc Zyngier wrote: > > We cannot tell from the S2 attributes whether what we map is memory > > or not when S2_AS_S1 is set, and issuing a CMO on device memory may > > not be the best idea. > > > > In this particular case, pretend that the mapping isn't cacheable. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/hyp/pgtable.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index 3c5f399b1b986..07561a227f75e 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -911,6 +911,14 @@ static void stage2_unmap_put_pte(const struct kvm_pgtable_visit_ctx *ctx, > > static bool stage2_pte_cacheable(struct kvm_pgtable *pgt, kvm_pte_t pte) > > { > > u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; > > + > > + /* > > + * With S2_AS_S1, we have no idea whether the OA is actual memory or > > + * a device. Don't even try a CMO on that. > > + */ > > + if (pgt->flags & KVM_PGTABLE_S2_AS_S1) > > + return false; > > + > > return kvm_pte_valid(pte) && memattr == KVM_S2_MEMATTR(pgt, NORMAL); > > Since KVM_PGTABLE_S2_AS_S1 is only set for the pKVM host stage-2 and > that doesn't provide any cache maintenance callbacks in its > kvm_pgtable_mm_ops, I don't think the current code is actually broken, Frankly, I have no idea how I came to such a stupid conclusion. My only way out is to blame Metallica (don't listen to that shit, kids!). > although it's harmless to add the check (and the comment might benefit > from some additional rewording?). I don't think there is much value in adding something that is not useful. I'll drop that patch altogether. Thanks, M. -- Without deviation from the norm, progress is not possible.