From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, T_DKIMWL_WL_HIGH,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AC6DC04AB5 for ; Thu, 6 Jun 2019 07:18:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B69AA2083D for ; Thu, 6 Jun 2019 07:18:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fUbrBtDj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B69AA2083D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bDZ1DPJwgdXsv8d9TWnYoY70Aj/oQBEvuSuAmdC1u9s=; b=fUbrBtDjkn/zZz 18gtNPcm6d2ObP9xk11OfE1wcqQ46tXQT/l3ZkfOyF0hutF/hlCfFWSp089lzFTNGi5a9HWrdTJ0x F0Q1+lteno3LDHMQCnPWK+oEv0XuVUYjmeRGOHWYHP3u1vjrZOY0p9+vPrMU9mjolMky3W4nzxRG9 4Ri8Op7vXJ5EJVS/RBylZz8ujbFbbdfn2t+x0b/XZJhSFdMpQe5Ep7bBScaHLULJSvfw7Uxn1/1ll NfMHncz+2esI8zgm8evFSZsvED8IXZtC7OVG4LTAI5SdCn+RHF+Af/oPqUHUQZ+UxIuIcguKg25u3 Hj83EO+kBy+Rk3V2xyjA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hYmfV-0002ty-8v; Thu, 06 Jun 2019 07:18:37 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hYmfS-0002t3-LA for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2019 07:18:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6F5F374; Thu, 6 Jun 2019 00:18:31 -0700 (PDT) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C25143F246; Thu, 6 Jun 2019 00:18:28 -0700 (PDT) Date: Thu, 06 Jun 2019 08:18:25 +0100 Message-ID: <86lfyfgp1a.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Bharat Kumar Gogada Subject: Re: [PATCH v3] PCI: xilinx-nwl: Fix Multi MSI data programming In-Reply-To: References: <1559133469-11981-1-git-send-email-bharat.kumar.gogada@xilinx.com> <20190531160956.GB9356@redmoon> <5de53585-e90f-77d2-bd96-025e1b39a573@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190606_001834_703753_F4138785 X-CRM114-Status: GOOD ( 23.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "lorenzo.pieralisi@arm.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Ravikiran Gummaluri , "bhelgaas@google.com" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 06 Jun 2019 05:49:45 +0100, Bharat Kumar Gogada wrote: > > > On 31/05/2019 17:09, Lorenzo Pieralisi wrote: > > > [+Marc] > > > > > > On Wed, May 29, 2019 at 06:07:49PM +0530, Bharat Kumar Gogada wrote: > > >> The current Multi MSI data programming fails if multiple end points > > >> requesting MSI and multi MSI are connected with switch, i.e the > > >> current multi MSI data being given is not considering the number of > > >> vectors being requested in case of multi MSI. > > >> Ex: Two EP's connected via switch, EP1 requesting single MSI first, > > >> EP2 requesting Multi MSI of count four. The current code gives MSI > > >> data 0x0 to EP1 and 0x1 to EP2, but EP2 can modify lower two bits due > > >> to which EP2 also sends interrupt with MSI data 0x0 which results in > > >> always invoking virq of EP1 due to which EP2 MSI interrupt never gets > > >> handled. > > > > > > If this is a problem it is not the only driver where it should be > > > fixed it seems. CC'ed Marc in case I have missed something in relation > > > to MSI IRQs but AFAIU it looks like HW is allowed to toggled bits > > > (according to bits[6:4] in Message Control for MSI) in the MSI data, > > > given that the data written is the hwirq number (in this specific MSI > > > controller) it ought to be fixed. > > > > Yeah, it looks like a number of MSI controllers could be quite broken in this > > particular area. > > > > > > > > The commit log and patch should be rewritten (I will do that) but > > > first I would like to understand if there are more drivers to be > > > updated. > > > > > > > Hi Lorenzo and Marc, thanks for your time. > Marc, I'm yet to test the below suggested solution, > GIC v2m and GIC v3 supports multi MSI, do we see above issue in > these MSI controllers ? To the best of my knowledge, these drivers do support MultiMSI correctly. GICv2m actually gained the support pretty recently (see de337ee30142). The GICv3 ITS never ha an issue with that, given that per device EventIDs are always 0-based. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel