From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD6CDCD4F54 for ; Wed, 27 May 2026 10:52:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Subject:Cc:To:From:Message-ID:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4XE3jVKRLJiqOr507V6y6IObkBgPaGSpBZ4Jf9AwYyU=; b=AROJ2Hp6nEdEwqBbGfLSOB7Wju R8jCcfaHBl8knogEEpMQEssFqMM8f9w25ZqMTXOIT1S/Fn8+Hu7B6HH1gsIuCdU0MILlVDPA0jALe pdVvso3nJM1okwpbp2HNGerq5M+ZUi3o9v/ckH3vDP0cRhGfeP2/yGFoCJmnPmm/tDmcw1I79+EqB u76uUh7ehImMYbj8B3ygMEh34eEtvXLZZu9c+Ooq6cOUGkwYsK0Kw3yn2+B0B2mXYlJuqX1UCi6Pa pp6dKm5BQm3HzI14Fjdf2cEK+RzL8kMNPAJCUsuJGSvkRvuOAp3p71LNTIpDRdd9QpQnwLZ+bCB4G CzgJqWIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wSBrk-00000003y0y-0r7V; Wed, 27 May 2026 10:52:00 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wSBrf-00000003y0V-3hYL for linux-arm-kernel@lists.infradead.org; Wed, 27 May 2026 10:51:59 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 97AEA40294; Wed, 27 May 2026 10:51:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 796531F000E9; Wed, 27 May 2026 10:51:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779879115; bh=4XE3jVKRLJiqOr507V6y6IObkBgPaGSpBZ4Jf9AwYyU=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=VuZl16DhMrRvTzEXlDbYmB30nnzXbHxJEr9wgHJfAV54MODXeJtHyvOnxlfTCzNHh I+Znw4UR2Csu6hPkQ94IfX3sFW/3hja2r9YeCgr8bPdeOT5QCPyO7dTjH5327lo/AY 9mzgZXNqX8LhHaoP4HWJb/fu3vLBLoxN01pkT5L2HCkB/+20wPveXcaFukzzqSjLVd i33wQxVnk6OY8RC8Acp7OVZyNi6l3B7FN/kUcf4KMS3pTPR7cLSCN6XXDyrY6/UfsR q8D9s1Q4a/Qf1qSjj7ycN0McjNLFKoB6EZgzaUbS1wOABED05E5pR3sNGKZsneUqWH k+T+n6uuMv0RA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wSBrd-00000006dx0-2PbV; Wed, 27 May 2026 10:51:53 +0000 Date: Wed, 27 May 2026 11:51:53 +0100 Message-ID: <86mrxlunue.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH v2 03/39] irqchip/gic-v5: Setup gic_kvm_info on ACPI hosts In-Reply-To: <20260521144846.1899475-4-sascha.bischoff@arm.com> References: <20260521144846.1899475-1-sascha.bischoff@arm.com> <20260521144846.1899475-4-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260527_035155_964098_83FE02AF X-CRM114-Status: GOOD ( 32.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 21 May 2026 15:50:09 +0100, Sascha Bischoff wrote: > > Device-tree based GICv5 probing already passes the IRS details and > maintenance interrupt to KVM, but the ACPI path only initialises the > irqchip and installs the ACPI IRQ model. As a result, KVM never sees > the GICv5 host information required to probe the vGIC on ACPI systems. > > Add the ACPI equivalent of the DT KVM setup. Parse the MADT GICC > entries for the maintenance interrupt, require all relevant entries to > agree, register the interrupt as a GICv5 PPI-encoded GSI, and pass the > resulting IRQ together with the IRS base and coherency information to > KVM. Native GICv5 does not require a maintenance interrupt unless the > legacy GICv3-compatible CPU interface is present, so preserve the > existing no-maintenance-IRQ handling for that case. > > Signed-off-by: Sascha Bischoff > --- > drivers/irqchip/irq-gic-v5.c | 103 +++++++++++++++++++++++++++++++++-- > 1 file changed, 98 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c > index 707deabbf2f63..ccd1ec69a6ab2 100644 > --- a/drivers/irqchip/irq-gic-v5.c > +++ b/drivers/irqchip/irq-gic-v5.c > @@ -1126,7 +1126,7 @@ static void gicv5_set_cpuif_idbits(void) > #ifdef CONFIG_KVM > static struct gic_kvm_info gic_v5_kvm_info __initdata; > > -static void __init gic_of_setup_kvm_info(struct device_node *node) > +static void __init gic_setup_kvm_info(unsigned int maint_irq) > { > struct gicv5_irs_chip_data *irs_data = gicv5_irs_get_chip_data(); > > @@ -1140,13 +1140,14 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) > return; > } > > - gic_v5_kvm_info.type = GIC_V5; > + if (WARN_ON(!irs_data)) > + return; > > + gic_v5_kvm_info.type = GIC_V5; > gic_v5_kvm_info.gicv5_irs.base = irs_data->irs_base; > gic_v5_kvm_info.gicv5_irs.non_coherent = !!(irs_data->flags & IRS_FLAGS_NON_COHERENT); > - > - /* GIC Virtual CPU interface maintenance interrupt */ > - gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); > + gic_v5_kvm_info.maint_irq = maint_irq; > + gic_v5_kvm_info.no_maint_irq_mask = false; You remove this last line from patch #1, and reintroduce it here. My gut feeling is that it should never be removed the first place. > > /* > * We require an MI if we have legacy support, but don't, otherwise. > @@ -1162,10 +1163,101 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) > > vgic_set_kvm_info(&gic_v5_kvm_info); > } > + > +static void __init gic_of_setup_kvm_info(struct device_node *node) > +{ > + /* GIC Virtual CPU interface maintenance interrupt */ > + gic_setup_kvm_info(irq_of_parse_and_map(node, 0)); > +} > + > +#ifdef CONFIG_ACPI > +struct gicv5_acpi_kvm_info { > + u32 maint_irq; > + int maint_irq_mode; > +}; > + > +static struct gicv5_acpi_kvm_info acpi_v5_kvm_info __initdata; > + > +static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header, > + const unsigned long end) > +{ > + struct acpi_madt_generic_interrupt *gicc = > + (struct acpi_madt_generic_interrupt *)header; > + static int first_madt = true; > + int maint_irq_mode; > + > + if (!(gicc->flags & > + (ACPI_MADT_ENABLED | ACPI_MADT_GICC_ONLINE_CAPABLE))) > + return 0; > + > + maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? > + ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; > + > + if (first_madt) { > + first_madt = false; > + > + acpi_v5_kvm_info.maint_irq = gicc->vgic_interrupt; > + acpi_v5_kvm_info.maint_irq_mode = maint_irq_mode; > + return 0; > + } > + > + /* The maintenance interrupt must be the same for every GICC entry. */ > + if (acpi_v5_kvm_info.maint_irq != gicc->vgic_interrupt || > + acpi_v5_kvm_info.maint_irq_mode != maint_irq_mode) > + return -EINVAL; > + > + return 0; > +} > + > +static bool __init gic_acpi_collect_virt_info(void) > +{ > + int count; > + > + acpi_v5_kvm_info.maint_irq = 0; > + acpi_v5_kvm_info.maint_irq_mode = 0; > + > + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, > + gic_acpi_parse_virt_madt_gicc, 0); > + > + return count > 0; > +} > + > +static void __init gic_acpi_setup_kvm_info(void) > +{ > + unsigned int maint_irq = 0; > + int irq; > + > + if (!gic_acpi_collect_virt_info()) { > + pr_warn("Unable to get hardware information used for virtualization\n"); > + return; > + } > + > + if (acpi_v5_kvm_info.maint_irq) { > + u32 gsi = FIELD_PREP(GICV5_HWIRQ_TYPE, GICV5_HWIRQ_TYPE_PPI) | > + FIELD_PREP(GICV5_HWIRQ_ID, acpi_v5_kvm_info.maint_irq); > + > + irq = acpi_register_gsi(NULL, gsi, > + acpi_v5_kvm_info.maint_irq_mode, > + ACPI_ACTIVE_HIGH); > + if (irq <= 0) > + return; This probably deserves a bit of a warning. And maybe not completely fail the registration with KVM? Thanks, M. -- Without deviation from the norm, progress is not possible.