[PATCH v3 0/5] KVM: selftests: Add ID reg test, update headers

[PATCH v3 0/5] KVM: selftests: Add ID reg test, update headers

[Oliver Upton]

v2: https://lore.kernel.org/kvmarm/20231010011023.2497088-1-oliver.upton@linux.dev/

v2 -> v3:
 - Use the kernel's script/data for generating the header instad of a
   copy (broonie)

Jing Zhang (2):
  tools headers arm64: Update sysreg.h with kernel sources
  KVM: arm64: selftests: Test for setting ID register from usersapce

Oliver Upton (3):
  tools: arm64: Add a Makefile for generating sysreg-defs.h
  perf build: Generate arm64's sysreg-defs.h and add to include path
  KVM: selftests: Generate sysreg-defs.h and add to include path

 tools/arch/arm64/include/.gitignore           |   1 +
 tools/arch/arm64/include/asm/gpr-num.h        |  26 +
 tools/arch/arm64/include/asm/sysreg.h         | 839 ++++--------------
 tools/arch/arm64/tools/Makefile               |  38 +
 tools/perf/Makefile.perf                      |  15 +-
 tools/perf/util/Build                         |   2 +-
 tools/testing/selftests/kvm/Makefile          |  24 +-
 .../selftests/kvm/aarch64/aarch32_id_regs.c   |   4 +-
 .../selftests/kvm/aarch64/debug-exceptions.c  |  12 +-
 .../selftests/kvm/aarch64/page_fault_test.c   |   6 +-
 .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++
 .../selftests/kvm/lib/aarch64/processor.c     |   6 +-
 12 files changed, 785 insertions(+), 667 deletions(-)
 create mode 100644 tools/arch/arm64/include/.gitignore
 create mode 100644 tools/arch/arm64/include/asm/gpr-num.h
 create mode 100644 tools/arch/arm64/tools/Makefile
 create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c


base-commit: dafa493dd01d5992f1cb70b08d1741c3ab99e04a
-- 
2.42.0.609.gbb76f46606-goog


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[PATCH v3 1/5] tools: arm64: Add a Makefile for generating sysreg-defs.h

[Oliver Upton]

Use a common Makefile for generating sysreg-defs.h, which will soon be
needed by perf and KVM selftests. The naming scheme of the generated
macros is not expected to change, so just refer to the canonical
script/data in the kernel source rather than copying to tools.

Co-developed-by: Jing Zhang <jingzhangos@google.com>
Signed-off-by: Jing Zhang <jingzhangos@google.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
 tools/arch/arm64/include/.gitignore |  1 +
 tools/arch/arm64/tools/Makefile     | 38 +++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 tools/arch/arm64/include/.gitignore
 create mode 100644 tools/arch/arm64/tools/Makefile

diff --git a/tools/arch/arm64/include/.gitignore b/tools/arch/arm64/include/.gitignore
new file mode 100644
index 000000000000..9ab870da897d
--- /dev/null
+++ b/tools/arch/arm64/include/.gitignore
@@ -0,0 +1 @@
+generated/
diff --git a/tools/arch/arm64/tools/Makefile b/tools/arch/arm64/tools/Makefile
new file mode 100644
index 000000000000..f867e6036c62
--- /dev/null
+++ b/tools/arch/arm64/tools/Makefile
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0
+
+ifeq ($(srctree),)
+srctree := $(patsubst %/,%,$(dir $(CURDIR)))
+srctree := $(patsubst %/,%,$(dir $(srctree)))
+srctree := $(patsubst %/,%,$(dir $(srctree)))
+srctree := $(patsubst %/,%,$(dir $(srctree)))
+endif
+
+include $(srctree)/tools/scripts/Makefile.include
+
+AWK	?= awk
+MKDIR	?= mkdir
+RM	?= rm
+
+ifeq ($(V),1)
+Q =
+else
+Q = @
+endif
+
+arm64_tools_dir = $(srctree)/arch/arm64/tools
+arm64_sysreg_tbl = $(arm64_tools_dir)/sysreg
+arm64_gen_sysreg = $(arm64_tools_dir)/gen-sysreg.awk
+arm64_generated_dir = $(srctree)/tools/arch/arm64/include/generated
+arm64_sysreg_defs = $(arm64_generated_dir)/asm/sysreg-defs.h
+
+all: $(arm64_sysreg_defs)
+	@:
+
+$(arm64_sysreg_defs): $(arm64_gen_sysreg) $(arm64_sysreg_tbl)
+	$(Q)$(MKDIR) -p $(dir $@)
+	$(QUIET_GEN)$(AWK) -f $^ > $@
+
+clean:
+	$(Q)$(RM) -rf $(arm64_generated_dir)
+
+.PHONY: all clean
-- 
2.42.0.609.gbb76f46606-goog


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Re: [PATCH v3 1/5] tools: arm64: Add a Makefile for generating sysreg-defs.h

[Eric Auger]

Hi Oliver,

On 10/11/23 21:57, Oliver Upton wrote:
> Use a common Makefile for generating sysreg-defs.h, which will soon be
> needed by perf and KVM selftests. The naming scheme of the generated
> macros is not expected to change, so just refer to the canonical
> script/data in the kernel source rather than copying to tools.
> 
> Co-developed-by: Jing Zhang <jingzhangos@google.com>
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  tools/arch/arm64/include/.gitignore |  1 +
>  tools/arch/arm64/tools/Makefile     | 38 +++++++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
>  create mode 100644 tools/arch/arm64/include/.gitignore
>  create mode 100644 tools/arch/arm64/tools/Makefile
> 
> diff --git a/tools/arch/arm64/include/.gitignore b/tools/arch/arm64/include/.gitignore
> new file mode 100644
> index 000000000000..9ab870da897d
> --- /dev/null
> +++ b/tools/arch/arm64/include/.gitignore
> @@ -0,0 +1 @@
> +generated/
> diff --git a/tools/arch/arm64/tools/Makefile b/tools/arch/arm64/tools/Makefile
> new file mode 100644
> index 000000000000..f867e6036c62
> --- /dev/null
> +++ b/tools/arch/arm64/tools/Makefile
> @@ -0,0 +1,38 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +ifeq ($(srctree),)
> +srctree := $(patsubst %/,%,$(dir $(CURDIR)))
> +srctree := $(patsubst %/,%,$(dir $(srctree)))
> +srctree := $(patsubst %/,%,$(dir $(srctree)))
> +srctree := $(patsubst %/,%,$(dir $(srctree)))
> +endif
> +
> +include $(srctree)/tools/scripts/Makefile.include
> +
> +AWK	?= awk
> +MKDIR	?= mkdir
> +RM	?= rm
> +
> +ifeq ($(V),1)
> +Q =
> +else
> +Q = @
> +endif
> +
> +arm64_tools_dir = $(srctree)/arch/arm64/tools
> +arm64_sysreg_tbl = $(arm64_tools_dir)/sysreg
> +arm64_gen_sysreg = $(arm64_tools_dir)/gen-sysreg.awk
> +arm64_generated_dir = $(srctree)/tools/arch/arm64/include/generated
> +arm64_sysreg_defs = $(arm64_generated_dir)/asm/sysreg-defs.h
> +
> +all: $(arm64_sysreg_defs)
> +	@:
> +
> +$(arm64_sysreg_defs): $(arm64_gen_sysreg) $(arm64_sysreg_tbl)
> +	$(Q)$(MKDIR) -p $(dir $@)
> +	$(QUIET_GEN)$(AWK) -f $^ > $@
> +
> +clean:
> +	$(Q)$(RM) -rf $(arm64_generated_dir)
> +
> +.PHONY: all clean


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[PATCH v3 2/5] perf build: Generate arm64's sysreg-defs.h and add to include path

[Oliver Upton]

Start generating sysreg-defs.h in anticipation of updating sysreg.h to a
version that needs the generated output.

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
 tools/perf/Makefile.perf | 15 +++++++++++++--
 tools/perf/util/Build    |  2 +-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
index 37af6df7b978..14dedd11a1f5 100644
--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
@@ -443,6 +443,15 @@ drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
 # Create output directory if not already present
 _dummy := $(shell [ -d '$(beauty_ioctl_outdir)' ] || mkdir -p '$(beauty_ioctl_outdir)')
 
+arm64_gen_sysreg_dir := $(srctree)/tools/arch/arm64/tools
+
+arm64-sysreg-defs: FORCE
+	$(Q)$(MAKE) -C $(arm64_gen_sysreg_dir)
+
+arm64-sysreg-defs-clean:
+	$(call QUIET_CLEAN,arm64-sysreg-defs)
+	$(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) clean > /dev/null
+
 $(drm_ioctl_array): $(drm_hdr_dir)/drm.h $(drm_hdr_dir)/i915_drm.h $(drm_ioctl_tbl)
 	$(Q)$(SHELL) '$(drm_ioctl_tbl)' $(drm_hdr_dir) > $@
 
@@ -716,7 +725,9 @@ endif
 __build-dir = $(subst $(OUTPUT),,$(dir $@))
 build-dir   = $(or $(__build-dir),.)
 
-prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders $(drm_ioctl_array) \
+prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders \
+	arm64-sysreg-defs \
+	$(drm_ioctl_array) \
 	$(fadvise_advice_array) \
 	$(fsconfig_arrays) \
 	$(fsmount_arrays) \
@@ -1125,7 +1136,7 @@ endif # BUILD_BPF_SKEL
 bpf-skel-clean:
 	$(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS)
 
-clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
+clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
 	$(call QUIET_CLEAN, core-objs)  $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive $(OUTPUT)perf-iostat $(LANG_BINDINGS)
 	$(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete
 	$(Q)$(RM) $(OUTPUT).config-detected
diff --git a/tools/perf/util/Build b/tools/perf/util/Build
index 6d657c9927f7..2f76230958ad 100644
--- a/tools/perf/util/Build
+++ b/tools/perf/util/Build
@@ -345,7 +345,7 @@ CFLAGS_rbtree.o        += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ET
 CFLAGS_libstring.o     += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
 CFLAGS_hweight.o       += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
 CFLAGS_header.o        += -include $(OUTPUT)PERF-VERSION-FILE
-CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/
+CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/ -I$(srctree)/tools/arch/arm64/include/generated/
 
 $(OUTPUT)util/argv_split.o: ../lib/argv_split.c FORCE
 	$(call rule_mkdir)
-- 
2.42.0.609.gbb76f46606-goog


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Re: [PATCH v3 2/5] perf build: Generate arm64's sysreg-defs.h and add to include path

[Namhyung Kim]

Hello,

On Wed, Oct 11, 2023 at 12:58 PM Oliver Upton <oliver.upton@linux.dev> wrote:
>
> Start generating sysreg-defs.h in anticipation of updating sysreg.h to a
> version that needs the generated output.
>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

It seems we also need this on non-ARM archs to process ARM SPE data.

Acked-by: Namhyung Kim <namhyung@kernel.org>

Thanks,
Namhyung


> ---
>  tools/perf/Makefile.perf | 15 +++++++++++++--
>  tools/perf/util/Build    |  2 +-
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
> index 37af6df7b978..14dedd11a1f5 100644
> --- a/tools/perf/Makefile.perf
> +++ b/tools/perf/Makefile.perf
> @@ -443,6 +443,15 @@ drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
>  # Create output directory if not already present
>  _dummy := $(shell [ -d '$(beauty_ioctl_outdir)' ] || mkdir -p '$(beauty_ioctl_outdir)')
>
> +arm64_gen_sysreg_dir := $(srctree)/tools/arch/arm64/tools
> +
> +arm64-sysreg-defs: FORCE
> +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir)
> +
> +arm64-sysreg-defs-clean:
> +       $(call QUIET_CLEAN,arm64-sysreg-defs)
> +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) clean > /dev/null
> +
>  $(drm_ioctl_array): $(drm_hdr_dir)/drm.h $(drm_hdr_dir)/i915_drm.h $(drm_ioctl_tbl)
>         $(Q)$(SHELL) '$(drm_ioctl_tbl)' $(drm_hdr_dir) > $@
>
> @@ -716,7 +725,9 @@ endif
>  __build-dir = $(subst $(OUTPUT),,$(dir $@))
>  build-dir   = $(or $(__build-dir),.)
>
> -prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders $(drm_ioctl_array) \
> +prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders \
> +       arm64-sysreg-defs \
> +       $(drm_ioctl_array) \
>         $(fadvise_advice_array) \
>         $(fsconfig_arrays) \
>         $(fsmount_arrays) \
> @@ -1125,7 +1136,7 @@ endif # BUILD_BPF_SKEL
>  bpf-skel-clean:
>         $(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS)
>
> -clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
> +clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
>         $(call QUIET_CLEAN, core-objs)  $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive $(OUTPUT)perf-iostat $(LANG_BINDINGS)
>         $(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete
>         $(Q)$(RM) $(OUTPUT).config-detected
> diff --git a/tools/perf/util/Build b/tools/perf/util/Build
> index 6d657c9927f7..2f76230958ad 100644
> --- a/tools/perf/util/Build
> +++ b/tools/perf/util/Build
> @@ -345,7 +345,7 @@ CFLAGS_rbtree.o        += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ET
>  CFLAGS_libstring.o     += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
>  CFLAGS_hweight.o       += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
>  CFLAGS_header.o        += -include $(OUTPUT)PERF-VERSION-FILE
> -CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/
> +CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/ -I$(srctree)/tools/arch/arm64/include/generated/
>
>  $(OUTPUT)util/argv_split.o: ../lib/argv_split.c FORCE
>         $(call rule_mkdir)
> --
> 2.42.0.609.gbb76f46606-goog
>

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Re: [PATCH v3 2/5] perf build: Generate arm64's sysreg-defs.h and add to include path

[Arnaldo Carvalho de Melo]

Em Tue, Oct 17, 2023 at 03:23:40PM -0700, Namhyung Kim escreveu:
> Hello,
> 
> On Wed, Oct 11, 2023 at 12:58 PM Oliver Upton <oliver.upton@linux.dev> wrote:
> >
> > Start generating sysreg-defs.h in anticipation of updating sysreg.h to a
> > version that needs the generated output.
> >
> > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> 
> It seems we also need this on non-ARM archs to process ARM SPE data.
> 
> Acked-by: Namhyung Kim <namhyung@kernel.org>

When building with CORESIGHT=1, yes.

I have it in my tests and:

⬢[acme@toolbox perf-tools-next]$ ls -la /tmp/build/perf-tools-next/util/arm-spe.o
-rw-r--r--. 1 acme acme 135432 Oct 17 16:49 /tmp/build/perf-tools-next/util/arm-spe.o
⬢[acme@toolbox perf-tools-next]$ ldd /tmp/build/perf-tools-next/perf | grep csd
	libopencsd_c_api.so.1 => /lib64/libopencsd_c_api.so.1 (0x00007f36bfca5000)
	libopencsd.so.1 => /lib64/libopencsd.so.1 (0x00007f36be2e0000)
⬢[acme@toolbox perf-tools-next]$ rpm -qf /lib64/libopencsd.so.1
opencsd-1.3.3-1.fc38.x86_64
⬢[acme@toolbox perf-tools-next]$ rpm -q --qf "%{summary}\n" opencsd
An open source CoreSight(tm) Trace Decode library
⬢[acme@toolbox perf-tools-next]$

Well, double checked and arm-spe.o is built by default, only way to
disable it is using NO_AUXTRACE=1 in the make command line, but then
IIRC one needs linking with opencsd to decode all those traces, right?

Anyway:

Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com>

- Arnaldo
 
> Thanks,
> Namhyung
> 
> 
> > ---
> >  tools/perf/Makefile.perf | 15 +++++++++++++--
> >  tools/perf/util/Build    |  2 +-
> >  2 files changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
> > index 37af6df7b978..14dedd11a1f5 100644
> > --- a/tools/perf/Makefile.perf
> > +++ b/tools/perf/Makefile.perf
> > @@ -443,6 +443,15 @@ drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
> >  # Create output directory if not already present
> >  _dummy := $(shell [ -d '$(beauty_ioctl_outdir)' ] || mkdir -p '$(beauty_ioctl_outdir)')
> >
> > +arm64_gen_sysreg_dir := $(srctree)/tools/arch/arm64/tools
> > +
> > +arm64-sysreg-defs: FORCE
> > +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir)
> > +
> > +arm64-sysreg-defs-clean:
> > +       $(call QUIET_CLEAN,arm64-sysreg-defs)
> > +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) clean > /dev/null
> > +
> >  $(drm_ioctl_array): $(drm_hdr_dir)/drm.h $(drm_hdr_dir)/i915_drm.h $(drm_ioctl_tbl)
> >         $(Q)$(SHELL) '$(drm_ioctl_tbl)' $(drm_hdr_dir) > $@
> >
> > @@ -716,7 +725,9 @@ endif
> >  __build-dir = $(subst $(OUTPUT),,$(dir $@))
> >  build-dir   = $(or $(__build-dir),.)
> >
> > -prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders $(drm_ioctl_array) \
> > +prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders \
> > +       arm64-sysreg-defs \
> > +       $(drm_ioctl_array) \
> >         $(fadvise_advice_array) \
> >         $(fsconfig_arrays) \
> >         $(fsmount_arrays) \
> > @@ -1125,7 +1136,7 @@ endif # BUILD_BPF_SKEL
> >  bpf-skel-clean:
> >         $(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS)
> >
> > -clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
> > +clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
> >         $(call QUIET_CLEAN, core-objs)  $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive $(OUTPUT)perf-iostat $(LANG_BINDINGS)
> >         $(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete
> >         $(Q)$(RM) $(OUTPUT).config-detected
> > diff --git a/tools/perf/util/Build b/tools/perf/util/Build
> > index 6d657c9927f7..2f76230958ad 100644
> > --- a/tools/perf/util/Build
> > +++ b/tools/perf/util/Build
> > @@ -345,7 +345,7 @@ CFLAGS_rbtree.o        += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ET
> >  CFLAGS_libstring.o     += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
> >  CFLAGS_hweight.o       += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
> >  CFLAGS_header.o        += -include $(OUTPUT)PERF-VERSION-FILE
> > -CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/
> > +CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/ -I$(srctree)/tools/arch/arm64/include/generated/
> >
> >  $(OUTPUT)util/argv_split.o: ../lib/argv_split.c FORCE
> >         $(call rule_mkdir)
> > --
> > 2.42.0.609.gbb76f46606-goog
> >

-- 

- Arnaldo

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Re: [PATCH v3 2/5] perf build: Generate arm64's sysreg-defs.h and add to include path

[Ian Rogers]

On Wed, Oct 18, 2023 at 7:12 AM Arnaldo Carvalho de Melo
<acme@kernel.org> wrote:
>
> Em Tue, Oct 17, 2023 at 03:23:40PM -0700, Namhyung Kim escreveu:
> > Hello,
> >
> > On Wed, Oct 11, 2023 at 12:58 PM Oliver Upton <oliver.upton@linux.dev> wrote:
> > >
> > > Start generating sysreg-defs.h in anticipation of updating sysreg.h to a
> > > version that needs the generated output.
> > >
> > > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> >
> > It seems we also need this on non-ARM archs to process ARM SPE data.
> >
> > Acked-by: Namhyung Kim <namhyung@kernel.org>
>
> When building with CORESIGHT=1, yes.
>
> I have it in my tests and:
>
> ⬢[acme@toolbox perf-tools-next]$ ls -la /tmp/build/perf-tools-next/util/arm-spe.o
> -rw-r--r--. 1 acme acme 135432 Oct 17 16:49 /tmp/build/perf-tools-next/util/arm-spe.o
> ⬢[acme@toolbox perf-tools-next]$ ldd /tmp/build/perf-tools-next/perf | grep csd
>         libopencsd_c_api.so.1 => /lib64/libopencsd_c_api.so.1 (0x00007f36bfca5000)
>         libopencsd.so.1 => /lib64/libopencsd.so.1 (0x00007f36be2e0000)
> ⬢[acme@toolbox perf-tools-next]$ rpm -qf /lib64/libopencsd.so.1
> opencsd-1.3.3-1.fc38.x86_64
> ⬢[acme@toolbox perf-tools-next]$ rpm -q --qf "%{summary}\n" opencsd
> An open source CoreSight(tm) Trace Decode library
> ⬢[acme@toolbox perf-tools-next]$
>
> Well, double checked and arm-spe.o is built by default, only way to
> disable it is using NO_AUXTRACE=1 in the make command line, but then
> IIRC one needs linking with opencsd to decode all those traces, right?
>
> Anyway:
>
> Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> - Arnaldo
>
> > Thanks,
> > Namhyung
> >
> >
> > > ---
> > >  tools/perf/Makefile.perf | 15 +++++++++++++--
> > >  tools/perf/util/Build    |  2 +-
> > >  2 files changed, 14 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
> > > index 37af6df7b978..14dedd11a1f5 100644
> > > --- a/tools/perf/Makefile.perf
> > > +++ b/tools/perf/Makefile.perf
> > > @@ -443,6 +443,15 @@ drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
> > >  # Create output directory if not already present
> > >  _dummy := $(shell [ -d '$(beauty_ioctl_outdir)' ] || mkdir -p '$(beauty_ioctl_outdir)')
> > >
> > > +arm64_gen_sysreg_dir := $(srctree)/tools/arch/arm64/tools
> > > +
> > > +arm64-sysreg-defs: FORCE
> > > +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir)

Should this not build an install_headers target? The generated code is
going into the source tree as is, ignoring O= options to make.

Thanks,
Ian

> > > +
> > > +arm64-sysreg-defs-clean:
> > > +       $(call QUIET_CLEAN,arm64-sysreg-defs)
> > > +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir) clean > /dev/null
> > > +
> > >  $(drm_ioctl_array): $(drm_hdr_dir)/drm.h $(drm_hdr_dir)/i915_drm.h $(drm_ioctl_tbl)
> > >         $(Q)$(SHELL) '$(drm_ioctl_tbl)' $(drm_hdr_dir) > $@
> > >
> > > @@ -716,7 +725,9 @@ endif
> > >  __build-dir = $(subst $(OUTPUT),,$(dir $@))
> > >  build-dir   = $(or $(__build-dir),.)
> > >
> > > -prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders $(drm_ioctl_array) \
> > > +prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders \
> > > +       arm64-sysreg-defs \
> > > +       $(drm_ioctl_array) \
> > >         $(fadvise_advice_array) \
> > >         $(fsconfig_arrays) \
> > >         $(fsmount_arrays) \
> > > @@ -1125,7 +1136,7 @@ endif # BUILD_BPF_SKEL
> > >  bpf-skel-clean:
> > >         $(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS)
> > >
> > > -clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
> > > +clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-clean $(LIBPERF)-clean arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean tests-coresight-targets-clean
> > >         $(call QUIET_CLEAN, core-objs)  $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive $(OUTPUT)perf-iostat $(LANG_BINDINGS)
> > >         $(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.cmd' -delete -o -name '\.*.d' -delete
> > >         $(Q)$(RM) $(OUTPUT).config-detected
> > > diff --git a/tools/perf/util/Build b/tools/perf/util/Build
> > > index 6d657c9927f7..2f76230958ad 100644
> > > --- a/tools/perf/util/Build
> > > +++ b/tools/perf/util/Build
> > > @@ -345,7 +345,7 @@ CFLAGS_rbtree.o        += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ET
> > >  CFLAGS_libstring.o     += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
> > >  CFLAGS_hweight.o       += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))"
> > >  CFLAGS_header.o        += -include $(OUTPUT)PERF-VERSION-FILE
> > > -CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/
> > > +CFLAGS_arm-spe.o       += -I$(srctree)/tools/arch/arm64/include/ -I$(srctree)/tools/arch/arm64/include/generated/
> > >
> > >  $(OUTPUT)util/argv_split.o: ../lib/argv_split.c FORCE
> > >         $(call rule_mkdir)
> > > --
> > > 2.42.0.609.gbb76f46606-goog
> > >
>
> --
>
> - Arnaldo

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Re: [PATCH v3 2/5] perf build: Generate arm64's sysreg-defs.h and add to include path

[Ian Rogers]

On Mon, Nov 6, 2023 at 10:10 PM Ian Rogers <irogers@google.com> wrote:
>
> On Wed, Oct 18, 2023 at 7:12 AM Arnaldo Carvalho de Melo
> <acme@kernel.org> wrote:
> >
> > Em Tue, Oct 17, 2023 at 03:23:40PM -0700, Namhyung Kim escreveu:
> > > Hello,
> > >
> > > On Wed, Oct 11, 2023 at 12:58 PM Oliver Upton <oliver.upton@linux.dev> wrote:
> > > >
> > > > Start generating sysreg-defs.h in anticipation of updating sysreg.h to a
> > > > version that needs the generated output.
> > > >
> > > > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> > >
> > > It seems we also need this on non-ARM archs to process ARM SPE data.
> > >
> > > Acked-by: Namhyung Kim <namhyung@kernel.org>
> >
> > When building with CORESIGHT=1, yes.
> >
> > I have it in my tests and:
> >
> > ⬢[acme@toolbox perf-tools-next]$ ls -la /tmp/build/perf-tools-next/util/arm-spe.o
> > -rw-r--r--. 1 acme acme 135432 Oct 17 16:49 /tmp/build/perf-tools-next/util/arm-spe.o
> > ⬢[acme@toolbox perf-tools-next]$ ldd /tmp/build/perf-tools-next/perf | grep csd
> >         libopencsd_c_api.so.1 => /lib64/libopencsd_c_api.so.1 (0x00007f36bfca5000)
> >         libopencsd.so.1 => /lib64/libopencsd.so.1 (0x00007f36be2e0000)
> > ⬢[acme@toolbox perf-tools-next]$ rpm -qf /lib64/libopencsd.so.1
> > opencsd-1.3.3-1.fc38.x86_64
> > ⬢[acme@toolbox perf-tools-next]$ rpm -q --qf "%{summary}\n" opencsd
> > An open source CoreSight(tm) Trace Decode library
> > ⬢[acme@toolbox perf-tools-next]$
> >
> > Well, double checked and arm-spe.o is built by default, only way to
> > disable it is using NO_AUXTRACE=1 in the make command line, but then
> > IIRC one needs linking with opencsd to decode all those traces, right?
> >
> > Anyway:
> >
> > Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> >
> > - Arnaldo
> >
> > > Thanks,
> > > Namhyung
> > >
> > >
> > > > ---
> > > >  tools/perf/Makefile.perf | 15 +++++++++++++--
> > > >  tools/perf/util/Build    |  2 +-
> > > >  2 files changed, 14 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
> > > > index 37af6df7b978..14dedd11a1f5 100644
> > > > --- a/tools/perf/Makefile.perf
> > > > +++ b/tools/perf/Makefile.perf
> > > > @@ -443,6 +443,15 @@ drm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/drm_ioctl.sh
> > > >  # Create output directory if not already present
> > > >  _dummy := $(shell [ -d '$(beauty_ioctl_outdir)' ] || mkdir -p '$(beauty_ioctl_outdir)')
> > > >
> > > > +arm64_gen_sysreg_dir := $(srctree)/tools/arch/arm64/tools
> > > > +
> > > > +arm64-sysreg-defs: FORCE
> > > > +       $(Q)$(MAKE) -C $(arm64_gen_sysreg_dir)
>
> Should this not build an install_headers target? The generated code is
> going into the source tree as is, ignoring O= options to make.

I think on top of this, tools/perf/MANIFEST needs to have:
arch/arm64/tools/gen-sysreg.awk
arch/arm64/tools/sysreg
This will add these files to the release tar balls, it already
contains things like scripts/bpf_doc.py.
tools/arch/arm64/tools/Makefile is picked up by tools/arch being in
the MANIFEST.

Thanks,
Ian

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[PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Oliver Upton]

Start generating sysreg-defs.h for arm64 builds in anticipation of
updating sysreg.h to a version that depends on it.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
 tools/testing/selftests/kvm/Makefile | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index a3bb36fb3cfc..07b3f4dc1a77 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -17,6 +17,17 @@ else
 	ARCH_DIR := $(ARCH)
 endif
 
+ifeq ($(ARCH),arm64)
+arm64_tools_dir := $(top_srcdir)/tools/arch/arm64/tools/
+GEN_HDRS := $(top_srcdir)/tools/arch/arm64/include/generated/
+CFLAGS += -I$(GEN_HDRS)
+
+prepare:
+	$(MAKE) -C $(arm64_tools_dir)
+else
+prepare:
+endif
+
 LIBKVM += lib/assert.c
 LIBKVM += lib/elf.c
 LIBKVM += lib/guest_modes.c
@@ -256,13 +267,18 @@ $(TEST_GEN_OBJ): $(OUTPUT)/%.o: %.c
 $(SPLIT_TESTS_TARGETS): %: %.o $(SPLIT_TESTS_OBJS)
 	$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH) $^ $(LDLIBS) -o $@
 
-EXTRA_CLEAN += $(LIBKVM_OBJS) $(TEST_DEP_FILES) $(TEST_GEN_OBJ) $(SPLIT_TESTS_OBJS) cscope.*
+EXTRA_CLEAN += $(GEN_HDRS) \
+	       $(LIBKVM_OBJS) \
+	       $(SPLIT_TESTS_OBJS) \
+	       $(TEST_DEP_FILES) \
+	       $(TEST_GEN_OBJ) \
+	       cscope.*
 
 x := $(shell mkdir -p $(sort $(dir $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ))))
-$(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c
+$(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c prepare
 	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
 
-$(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S
+$(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S prepare
 	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
 
 # Compile the string overrides as freestanding to prevent the compiler from
@@ -274,6 +290,7 @@ $(LIBKVM_STRING_OBJ): $(OUTPUT)/%.o: %.c
 x := $(shell mkdir -p $(sort $(dir $(TEST_GEN_PROGS))))
 $(TEST_GEN_PROGS): $(LIBKVM_OBJS)
 $(TEST_GEN_PROGS_EXTENDED): $(LIBKVM_OBJS)
+$(TEST_GEN_OBJ): prepare
 
 cscope: include_paths = $(LINUX_TOOL_INCLUDE) $(LINUX_HDR_PATH) include lib ..
 cscope:
-- 
2.42.0.609.gbb76f46606-goog


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Re: [PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Eric Auger]

Hi Oliver,

On 10/11/23 21:57, Oliver Upton wrote:
> Start generating sysreg-defs.h for arm64 builds in anticipation of
> updating sysreg.h to a version that depends on it.
> 
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eric

> ---
>  tools/testing/selftests/kvm/Makefile | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index a3bb36fb3cfc..07b3f4dc1a77 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -17,6 +17,17 @@ else
>  	ARCH_DIR := $(ARCH)
>  endif
>  
> +ifeq ($(ARCH),arm64)
> +arm64_tools_dir := $(top_srcdir)/tools/arch/arm64/tools/
> +GEN_HDRS := $(top_srcdir)/tools/arch/arm64/include/generated/
> +CFLAGS += -I$(GEN_HDRS)
> +
> +prepare:
> +	$(MAKE) -C $(arm64_tools_dir)
> +else
> +prepare:
> +endif
> +
>  LIBKVM += lib/assert.c
>  LIBKVM += lib/elf.c
>  LIBKVM += lib/guest_modes.c
> @@ -256,13 +267,18 @@ $(TEST_GEN_OBJ): $(OUTPUT)/%.o: %.c
>  $(SPLIT_TESTS_TARGETS): %: %.o $(SPLIT_TESTS_OBJS)
>  	$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH) $^ $(LDLIBS) -o $@
>  
> -EXTRA_CLEAN += $(LIBKVM_OBJS) $(TEST_DEP_FILES) $(TEST_GEN_OBJ) $(SPLIT_TESTS_OBJS) cscope.*
> +EXTRA_CLEAN += $(GEN_HDRS) \
> +	       $(LIBKVM_OBJS) \
> +	       $(SPLIT_TESTS_OBJS) \
> +	       $(TEST_DEP_FILES) \
> +	       $(TEST_GEN_OBJ) \
> +	       cscope.*
>  
>  x := $(shell mkdir -p $(sort $(dir $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ))))
> -$(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c
> +$(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c prepare
>  	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
>  
> -$(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S
> +$(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S prepare
>  	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
>  
>  # Compile the string overrides as freestanding to prevent the compiler from
> @@ -274,6 +290,7 @@ $(LIBKVM_STRING_OBJ): $(OUTPUT)/%.o: %.c
>  x := $(shell mkdir -p $(sort $(dir $(TEST_GEN_PROGS))))
>  $(TEST_GEN_PROGS): $(LIBKVM_OBJS)
>  $(TEST_GEN_PROGS_EXTENDED): $(LIBKVM_OBJS)
> +$(TEST_GEN_OBJ): prepare
>  
>  cscope: include_paths = $(LINUX_TOOL_INCLUDE) $(LINUX_HDR_PATH) include lib ..
>  cscope:


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Re: [PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Nina Schoetterl-Glausch]

On Wed, 2023-10-11 at 19:57 +0000, Oliver Upton wrote:
> Start generating sysreg-defs.h for arm64 builds in anticipation of
> updating sysreg.h to a version that depends on it.
> 
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  tools/testing/selftests/kvm/Makefile | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index a3bb36fb3cfc..07b3f4dc1a77 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -17,6 +17,17 @@ else
>  	ARCH_DIR := $(ARCH)
>  endif
> 
> +ifeq ($(ARCH),arm64)
> +arm64_tools_dir := $(top_srcdir)/tools/arch/arm64/tools/
> +GEN_HDRS := $(top_srcdir)/tools/arch/arm64/include/generated/
> +CFLAGS += -I$(GEN_HDRS)
> +
> +prepare:
> +	$(MAKE) -C $(arm64_tools_dir)
> +else
> +prepare:

This is a force target, all targets depending on this one will always have their recipe run,
so we'll pretty much rebuild everything.
Is this intentional?

> +endif
> +
>  LIBKVM += lib/assert.c
>  LIBKVM += lib/elf.c
>  LIBKVM += lib/guest_modes.c
> @@ -256,13 +267,18 @@ $(TEST_GEN_OBJ): $(OUTPUT)/%.o: %.c
>  $(SPLIT_TESTS_TARGETS): %: %.o $(SPLIT_TESTS_OBJS)
>  	$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH) $^ $(LDLIBS) -o $@
> 
> -EXTRA_CLEAN += $(LIBKVM_OBJS) $(TEST_DEP_FILES) $(TEST_GEN_OBJ) $(SPLIT_TESTS_OBJS) cscope.*
> +EXTRA_CLEAN += $(GEN_HDRS) \
> +	       $(LIBKVM_OBJS) \
> +	       $(SPLIT_TESTS_OBJS) \
> +	       $(TEST_DEP_FILES) \
> +	       $(TEST_GEN_OBJ) \
> +	       cscope.*
> 
>  x := $(shell mkdir -p $(sort $(dir $(LIBKVM_C_OBJ) $(LIBKVM_S_OBJ))))
> -$(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c
> +$(LIBKVM_C_OBJ): $(OUTPUT)/%.o: %.c prepare
>  	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
> 
> -$(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S
> +$(LIBKVM_S_OBJ): $(OUTPUT)/%.o: %.S prepare
>  	$(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
> 
>  # Compile the string overrides as freestanding to prevent the compiler from
> @@ -274,6 +290,7 @@ $(LIBKVM_STRING_OBJ): $(OUTPUT)/%.o: %.c
>  x := $(shell mkdir -p $(sort $(dir $(TEST_GEN_PROGS))))
>  $(TEST_GEN_PROGS): $(LIBKVM_OBJS)
>  $(TEST_GEN_PROGS_EXTENDED): $(LIBKVM_OBJS)
> +$(TEST_GEN_OBJ): prepare
> 
>  cscope: include_paths = $(LINUX_TOOL_INCLUDE) $(LINUX_HDR_PATH) include lib ..
>  cscope:


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Re: [PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Oliver Upton]

Hi Nina,

Apologies, I missed this email in my inbox and happened to see it on
lore.

On Mon, Oct 23, 2023 at 03:53:59PM +0200, Nina Schoetterl-Glausch wrote:

[...]

> > +ifeq ($(ARCH),arm64)
> > +arm64_tools_dir := $(top_srcdir)/tools/arch/arm64/tools/
> > +GEN_HDRS := $(top_srcdir)/tools/arch/arm64/include/generated/
> > +CFLAGS += -I$(GEN_HDRS)
> > +
> > +prepare:
> > +	$(MAKE) -C $(arm64_tools_dir)
> > +else
> > +prepare:
> 
> This is a force target, all targets depending on this one will always have their recipe run,
> so we'll pretty much rebuild everything.
> Is this intentional?

No, I just wasn't thinking about what I was doing :)

I've sent out a fix for this, plan to have it resolved before sending
out the PR for 6.7.

[*] https://lore.kernel.org/kvmarm/20231027005439.3142015-3-oliver.upton@linux.dev/

-- 
Thanks,
Oliver

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Re: [PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Aishwarya TCV]

On 11/10/2023 20:57, Oliver Upton wrote:
> Start generating sysreg-defs.h for arm64 builds in anticipation of
> updating sysreg.h to a version that depends on it.
> 
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  tools/testing/selftests/kvm/Makefile | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 

Hi Oliver,


Currently when building kselftest against next-master with arm64 arch
and defconfig+kselftest-kvm  “make[4]: *** [Makefile:26: prepare] Error
2” is observed.

The bisect log is below and a full log from a failing test job can be
seen here:

https://storage.kernelci.org/next/master/next-20231023/arm64/defconfig/gcc-10/logs/kselftest.log

make[4]: Entering directory '/tmp/kci/linux/tools/testing/selftests/kvm'
Makefile:270: warning: overriding recipe for target
'/tmp/kci/linux/build/kselftest/kvm/get-reg-list'
Makefile:265: warning: ignoring old recipe for target
'/tmp/kci/linux/build/kselftest/kvm/get-reg-list'
make -C ../../../../tools/arch/arm64/tools/
make[5]: Entering directory '/tmp/kci/linux/tools/arch/arm64/tools'
Makefile:10: ../tools/scripts/Makefile.include: No such file or directory
make[5]: *** No rule to make target '../tools/scripts/Makefile.include'.
 Stop.
make[5]: Leaving directory '/tmp/kci/linux/tools/arch/arm64/tools'
make[4]: *** [Makefile:26: prepare] Error 2
make[4]: Leaving directory '/tmp/kci/linux/tools/testing/selftests/kvm'

git bisect log
git bisect start
# good: [58720809f52779dc0f08e53e54b014209d13eebb] Linux 6.6-rc6
git bisect good 58720809f52779dc0f08e53e54b014209d13eebb
# bad: [4230ea146b1e64628f11e44290bb4008e391bc24] Add linux-next
specific files for 20231019
git bisect bad 4230ea146b1e64628f11e44290bb4008e391bc24
# good: [2958944f7786b88cb86f7b3377c1a8bda75fd506] Merge branch
'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
git bisect good 2958944f7786b88cb86f7b3377c1a8bda75fd506
# good: [359cb2003c0c273b13ec11b3df076ceac95e5eda] Merge branch
'for-next' of
https://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394.git
git bisect good 359cb2003c0c273b13ec11b3df076ceac95e5eda
# bad: [53cc85767a1dba86b892f72f18e44138ec5e3f83] Merge branch
'for-next' of
git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
git bisect bad 53cc85767a1dba86b892f72f18e44138ec5e3f83
# good: [84ceabd4408bd0bae48b58e2c18ddc5263cd5be4] Merge branch
'next-integrity' of
git://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity
git bisect good 84ceabd4408bd0bae48b58e2c18ddc5263cd5be4
# good: [35c2f21c0d4a633305773355e86b41e28d835f67] Merge branch 'master'
of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
git bisect good 35c2f21c0d4a633305773355e86b41e28d835f67
# bad: [92a288da516dc7aaab6e92ba3de7d51c415227b1] Merge branch
'topic/ppc-kvm' of
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
git bisect bad 92a288da516dc7aaab6e92ba3de7d51c415227b1
# good: [5df10099418f139bbf2f4e0d7b9a8727e76274ec] srcu: Explain why
callbacks invocations can't run concurrently
git bisect good 5df10099418f139bbf2f4e0d7b9a8727e76274ec
# good: [2ca9297790bdd24b4baa6e432d393e92272f7dc5] Merge branch
kvm-arm64/writable-id-regs into kvmarm/next
git bisect good 2ca9297790bdd24b4baa6e432d393e92272f7dc5
# good: [7ae3136edc0787c890e07fbd1d16d54557644068] Merge branch
'rcu/next' of
git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
git bisect good 7ae3136edc0787c890e07fbd1d16d54557644068
# bad: [50a1ee6541d7c7bac0a43b773b68f20c3ffcbe67] Merge branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
git bisect bad 50a1ee6541d7c7bac0a43b773b68f20c3ffcbe67
# bad: [54a9ea73527d55ab746d5425e10f3fa748e00e70] KVM: arm64: selftests:
Test for setting ID register from usersapce
git bisect bad 54a9ea73527d55ab746d5425e10f3fa748e00e70
# good: [e2bdd172e6652c2f5554d125a5048bc9f9b0dfa3] perf build: Generate
arm64's sysreg-defs.h and add to include path
git bisect good e2bdd172e6652c2f5554d125a5048bc9f9b0dfa3
# bad: [0359c946b13153bd57fac65f4f3600ba5673e3de] tools headers arm64:
Update sysreg.h with kernel sources
git bisect bad 0359c946b13153bd57fac65f4f3600ba5673e3de
# bad: [9697d84cc3b6d9bff4b1fbffc10a4bb1398af9ba] KVM: selftests:
Generate sysreg-defs.h and add to include path
git bisect bad 9697d84cc3b6d9bff4b1fbffc10a4bb1398af9ba
# first bad commit: [9697d84cc3b6d9bff4b1fbffc10a4bb1398af9ba] KVM:
selftests: Generate sysreg-defs.h and add to include path

Thanks,
Aishwarya

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Re: [PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Oliver Upton]

On Wed, Oct 25, 2023 at 10:02:36AM +0100, Aishwarya TCV wrote:
> On 11/10/2023 20:57, Oliver Upton wrote:
> > Start generating sysreg-defs.h for arm64 builds in anticipation of
> > updating sysreg.h to a version that depends on it.
> > 
> > Reviewed-by: Mark Brown <broonie@kernel.org>
> > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> > ---
> >  tools/testing/selftests/kvm/Makefile | 23 ++++++++++++++++++++---
> >  1 file changed, 20 insertions(+), 3 deletions(-)
> > 
> 
> Hi Oliver,
> 
> 
> Currently when building kselftest against next-master with arm64 arch
> and defconfig+kselftest-kvm  “make[4]: *** [Makefile:26: prepare] Error
> 2” is observed.

Looks like we're descending into tools/arch/arm64/tools/ w/
$(srctree) == ".", which I believe is coming from the top makefile. The
following diff fixes it for me, care to give it a go?

diff --git a/tools/arch/arm64/tools/Makefile b/tools/arch/arm64/tools/Makefile
index f867e6036c62..7f64b8bb5107 100644
--- a/tools/arch/arm64/tools/Makefile
+++ b/tools/arch/arm64/tools/Makefile
@@ -1,13 +1,13 @@
 # SPDX-License-Identifier: GPL-2.0
 
-ifeq ($(srctree),)
-srctree := $(patsubst %/,%,$(dir $(CURDIR)))
-srctree := $(patsubst %/,%,$(dir $(srctree)))
-srctree := $(patsubst %/,%,$(dir $(srctree)))
-srctree := $(patsubst %/,%,$(dir $(srctree)))
+ifeq ($(top_srcdir),)
+top_srcdir := $(patsubst %/,%,$(dir $(CURDIR)))
+top_srcdir := $(patsubst %/,%,$(dir $(top_srcdir)))
+top_srcdir := $(patsubst %/,%,$(dir $(top_srcdir)))
+top_srcdir := $(patsubst %/,%,$(dir $(top_srcdir)))
 endif
 
-include $(srctree)/tools/scripts/Makefile.include
+include $(top_srcdir)/tools/scripts/Makefile.include
 
 AWK	?= awk
 MKDIR	?= mkdir
@@ -19,10 +19,10 @@ else
 Q = @
 endif
 
-arm64_tools_dir = $(srctree)/arch/arm64/tools
+arm64_tools_dir = $(top_srcdir)/arch/arm64/tools
 arm64_sysreg_tbl = $(arm64_tools_dir)/sysreg
 arm64_gen_sysreg = $(arm64_tools_dir)/gen-sysreg.awk
-arm64_generated_dir = $(srctree)/tools/arch/arm64/include/generated
+arm64_generated_dir = $(top_srcdir)/tools/arch/arm64/include/generated
 arm64_sysreg_defs = $(arm64_generated_dir)/asm/sysreg-defs.h
 
 all: $(arm64_sysreg_defs)

-- 
Thanks,
Oliver

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Re: [PATCH v3 3/5] KVM: selftests: Generate sysreg-defs.h and add to include path

[Aishwarya TCV]

On 25/10/2023 20:07, Oliver Upton wrote:
> On Wed, Oct 25, 2023 at 10:02:36AM +0100, Aishwarya TCV wrote:
>> On 11/10/2023 20:57, Oliver Upton wrote:
>>> Start generating sysreg-defs.h for arm64 builds in anticipation of
>>> updating sysreg.h to a version that depends on it.
>>>
>>> Reviewed-by: Mark Brown <broonie@kernel.org>
>>> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
>>> ---
>>>  tools/testing/selftests/kvm/Makefile | 23 ++++++++++++++++++++---
>>>  1 file changed, 20 insertions(+), 3 deletions(-)
>>>
>>
>> Hi Oliver,
>>
>>
>> Currently when building kselftest against next-master with arm64 arch
>> and defconfig+kselftest-kvm  “make[4]: *** [Makefile:26: prepare] Error
>> 2” is observed.
> 
> Looks like we're descending into tools/arch/arm64/tools/ w/
> $(srctree) == ".", which I believe is coming from the top makefile. The
> following diff fixes it for me, care to give it a go?
> 
> diff --git a/tools/arch/arm64/tools/Makefile b/tools/arch/arm64/tools/Makefile
> index f867e6036c62..7f64b8bb5107 100644
> --- a/tools/arch/arm64/tools/Makefile
> +++ b/tools/arch/arm64/tools/Makefile

Confirming that the patch worked fine in the testing. Attached the log
below:

make[4]: Entering directory '/linux/tools/testing/selftests/kvm'
Makefile:270: warning: overriding recipe for target
'/linux/build-arm64/kselftest/kvm/get-reg-list'
Makefile:265: warning: ignoring old recipe for target
'/linux/build-arm64/kselftest/kvm/get-reg-list'
make -C ../../../../tools/arch/arm64/tools/
make[5]: Entering directory '/linux/tools/arch/arm64/tools'
  GEN     /linux/tools/arch/arm64/include/generated/asm/sysreg-defs.h
make[5]: Leaving directory '/linux/tools/arch/arm64/tools'

Thanks,
Aishwarya

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[PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Oliver Upton]

From: Jing Zhang <jingzhangos@google.com>

The users of sysreg.h (perf, KVM selftests) are now generating the
necessary sysreg-defs.h; sync sysreg.h with the kernel sources and
fix the KVM selftests that use macros which suffered a rename.

Signed-off-by: Jing Zhang <jingzhangos@google.com>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
 tools/arch/arm64/include/asm/gpr-num.h        |  26 +
 tools/arch/arm64/include/asm/sysreg.h         | 839 ++++--------------
 .../selftests/kvm/aarch64/aarch32_id_regs.c   |   4 +-
 .../selftests/kvm/aarch64/debug-exceptions.c  |  12 +-
 .../selftests/kvm/aarch64/page_fault_test.c   |   6 +-
 .../selftests/kvm/lib/aarch64/processor.c     |   6 +-
 6 files changed, 232 insertions(+), 661 deletions(-)
 create mode 100644 tools/arch/arm64/include/asm/gpr-num.h

diff --git a/tools/arch/arm64/include/asm/gpr-num.h b/tools/arch/arm64/include/asm/gpr-num.h
new file mode 100644
index 000000000000..05da4a7c5788
--- /dev/null
+++ b/tools/arch/arm64/include/asm/gpr-num.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_GPR_NUM_H
+#define __ASM_GPR_NUM_H
+
+#ifdef __ASSEMBLY__
+
+	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+	.equ	.L__gpr_num_x\num, \num
+	.equ	.L__gpr_num_w\num, \num
+	.endr
+	.equ	.L__gpr_num_xzr, 31
+	.equ	.L__gpr_num_wzr, 31
+
+#else /* __ASSEMBLY__ */
+
+#define __DEFINE_ASM_GPR_NUMS					\
+"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
+"	.equ	.L__gpr_num_x\\num, \\num\n"			\
+"	.equ	.L__gpr_num_w\\num, \\num\n"			\
+"	.endr\n"						\
+"	.equ	.L__gpr_num_xzr, 31\n"				\
+"	.equ	.L__gpr_num_wzr, 31\n"
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_GPR_NUM_H */
diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
index 7640fa27be94..ccc13e991376 100644
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@ -12,6 +12,8 @@
 #include <linux/bits.h>
 #include <linux/stringify.h>
 
+#include <asm/gpr-num.h>
+
 /*
  * ARMv8 ARM reserves the following encoding for system registers:
  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
@@ -87,20 +89,24 @@
  */
 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
 #define PSTATE_Imm_shift		CRm_shift
+#define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
 
 #define PSTATE_PAN			pstate_field(0, 4)
 #define PSTATE_UAO			pstate_field(0, 3)
 #define PSTATE_SSBS			pstate_field(3, 1)
+#define PSTATE_DIT			pstate_field(3, 2)
 #define PSTATE_TCO			pstate_field(3, 4)
 
-#define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
-#define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
-#define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
-#define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
+#define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
+#define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
+#define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
+#define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
 
 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
 #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
+#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
 
 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
@@ -108,25 +114,43 @@
 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
 
 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
+#define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
+#define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
+#define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
+#define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
+#define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
+#define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
+
+/*
+ * Automatically generated definitions for system registers, the
+ * manual encodings below are in the process of being converted to
+ * come from here. The header relies on the definition of sys_reg()
+ * earlier in this file.
+ */
+#include "asm/sysreg-defs.h"
 
 /*
  * System registers, organised loosely by encoding but grouped together
  * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
  */
-#define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
-#define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
-#define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
-#define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
-#define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
+#define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
+#define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
+#define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
+
 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
-#define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
+
 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
+#define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
+#define OSLSR_EL1_OSLM_NI		0
+#define OSLSR_EL1_OSLM_IMPLEMENTED	BIT(3)
+#define OSLSR_EL1_OSLK			BIT(1)
+
 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
@@ -142,59 +166,12 @@
 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
 
-#define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
-#define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
-#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
-#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
-#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
-#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
-#define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
-#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
-#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
-#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
-#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)
-
-#define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
-#define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
-#define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
-#define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
-#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
-#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
-#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
-
-#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
-#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
-#define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
-
-#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
-#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
-#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
-
-#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
-#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
-
-#define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
-#define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
-
-#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
-#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
-
-#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
-#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
-#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
-
-#define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
-#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
 
-#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
 
-#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
-#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
 
 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
@@ -230,159 +207,33 @@
 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
 
-#define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
 
 #define SYS_PAR_EL1_F			BIT(0)
 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
 
 /*** Statistical Profiling Extension ***/
-/* ID registers */
-#define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)
-#define SYS_PMSIDR_EL1_FE_SHIFT		0
-#define SYS_PMSIDR_EL1_FT_SHIFT		1
-#define SYS_PMSIDR_EL1_FL_SHIFT		2
-#define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3
-#define SYS_PMSIDR_EL1_LDS_SHIFT	4
-#define SYS_PMSIDR_EL1_ERND_SHIFT	5
-#define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8
-#define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL
-#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
-#define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL
-#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16
-#define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL
-
-#define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)
-#define SYS_PMBIDR_EL1_ALIGN_SHIFT	0
-#define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU
-#define SYS_PMBIDR_EL1_P_SHIFT		4
-#define SYS_PMBIDR_EL1_F_SHIFT		5
-
-/* Sampling controls */
-#define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)
-#define SYS_PMSCR_EL1_E0SPE_SHIFT	0
-#define SYS_PMSCR_EL1_E1SPE_SHIFT	1
-#define SYS_PMSCR_EL1_CX_SHIFT		3
-#define SYS_PMSCR_EL1_PA_SHIFT		4
-#define SYS_PMSCR_EL1_TS_SHIFT		5
-#define SYS_PMSCR_EL1_PCT_SHIFT		6
-
-#define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)
-#define SYS_PMSCR_EL2_E0HSPE_SHIFT	0
-#define SYS_PMSCR_EL2_E2SPE_SHIFT	1
-#define SYS_PMSCR_EL2_CX_SHIFT		3
-#define SYS_PMSCR_EL2_PA_SHIFT		4
-#define SYS_PMSCR_EL2_TS_SHIFT		5
-#define SYS_PMSCR_EL2_PCT_SHIFT		6
-
-#define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)
-
-#define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)
-#define SYS_PMSIRR_EL1_RND_SHIFT	0
-#define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8
-#define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL
-
-/* Filtering controls */
-#define SYS_PMSNEVFR_EL1		sys_reg(3, 0, 9, 9, 1)
-
-#define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)
-#define SYS_PMSFCR_EL1_FE_SHIFT		0
-#define SYS_PMSFCR_EL1_FT_SHIFT		1
-#define SYS_PMSFCR_EL1_FL_SHIFT		2
-#define SYS_PMSFCR_EL1_B_SHIFT		16
-#define SYS_PMSFCR_EL1_LD_SHIFT		17
-#define SYS_PMSFCR_EL1_ST_SHIFT		18
-
-#define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0_8_2	\
+#define PMSEVFR_EL1_RES0_IMP	\
 	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
-#define SYS_PMSEVFR_EL1_RES0_8_3	\
-	(SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
-
-#define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
-#define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
-
-/* Buffer controls */
-#define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)
-#define SYS_PMBLIMITR_EL1_E_SHIFT	0
-#define SYS_PMBLIMITR_EL1_FM_SHIFT	1
-#define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL
-#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
-
-#define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)
+#define PMSEVFR_EL1_RES0_V1P1	\
+	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
+#define PMSEVFR_EL1_RES0_V1P2	\
+	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
 
 /* Buffer error reporting */
-#define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)
-#define SYS_PMBSR_EL1_COLL_SHIFT	16
-#define SYS_PMBSR_EL1_S_SHIFT		17
-#define SYS_PMBSR_EL1_EA_SHIFT		18
-#define SYS_PMBSR_EL1_DL_SHIFT		19
-#define SYS_PMBSR_EL1_EC_SHIFT		26
-#define SYS_PMBSR_EL1_EC_MASK		0x3fUL
-
-#define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
-#define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
-#define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
-
-#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0
-#define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL
+#define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
+#define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
 
-#define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0
-#define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL
+#define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
+#define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
 
-#define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
+#define PMBSR_EL1_BUF_BSC_FULL		0x1UL
 
 /*** End of Statistical Profiling Extension ***/
 
-/*
- * TRBE Registers
- */
-#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
-#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
-#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
-#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
-#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
-#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
-#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
-
-#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
-#define TRBLIMITR_LIMIT_SHIFT		12
-#define TRBLIMITR_NVM			BIT(5)
-#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
-#define TRBLIMITR_TRIG_MODE_SHIFT	3
-#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
-#define TRBLIMITR_FILL_MODE_SHIFT	1
-#define TRBLIMITR_ENABLE		BIT(0)
-#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
-#define TRBPTR_PTR_SHIFT		0
-#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
-#define TRBBASER_BASE_SHIFT		12
-#define TRBSR_EC_MASK			GENMASK(5, 0)
-#define TRBSR_EC_SHIFT			26
-#define TRBSR_IRQ			BIT(22)
-#define TRBSR_TRG			BIT(21)
-#define TRBSR_WRAP			BIT(20)
-#define TRBSR_ABORT			BIT(18)
-#define TRBSR_STOP			BIT(17)
-#define TRBSR_MSS_MASK			GENMASK(15, 0)
-#define TRBSR_MSS_SHIFT			0
-#define TRBSR_BSC_MASK			GENMASK(5, 0)
-#define TRBSR_BSC_SHIFT			0
-#define TRBSR_FSC_MASK			GENMASK(5, 0)
-#define TRBSR_FSC_SHIFT			0
-#define TRBMAR_SHARE_MASK		GENMASK(1, 0)
-#define TRBMAR_SHARE_SHIFT		8
-#define TRBMAR_OUTER_MASK		GENMASK(3, 0)
-#define TRBMAR_OUTER_SHIFT		4
-#define TRBMAR_INNER_MASK		GENMASK(3, 0)
-#define TRBMAR_INNER_SHIFT		0
-#define TRBTRG_TRG_MASK			GENMASK(31, 0)
-#define TRBTRG_TRG_SHIFT		0
-#define TRBIDR_FLAG			BIT(5)
-#define TRBIDR_PROG			BIT(4)
-#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
-#define TRBIDR_ALIGN_SHIFT		0
+#define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
+#define TRBSR_EL1_BSC_SHIFT		0
 
 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
@@ -392,12 +243,6 @@
 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
 
-#define SYS_LORSA_EL1			sys_reg(3, 0, 10, 4, 0)
-#define SYS_LOREA_EL1			sys_reg(3, 0, 10, 4, 1)
-#define SYS_LORN_EL1			sys_reg(3, 0, 10, 4, 2)
-#define SYS_LORC_EL1			sys_reg(3, 0, 10, 4, 3)
-#define SYS_LORID_EL1			sys_reg(3, 0, 10, 4, 7)
-
 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
 
@@ -429,23 +274,10 @@
 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
 
-#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
-#define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
-
-#define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
-
 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
 
-#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
-#define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
-#define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
 
-#define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
-
-#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
-#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
-
 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 
@@ -465,6 +297,7 @@
 
 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
+#define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
 
 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
 
@@ -506,6 +339,10 @@
 
 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
 
+#define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
+#define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
+#define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
+
 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
@@ -515,7 +352,9 @@
 
 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
+#define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
+#define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
 
 #define __PMEV_op2(n)			((n) & 0x7)
 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
@@ -525,26 +364,48 @@
 
 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
 
+#define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
+#define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
+
 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
-#define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
-#define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
-#define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
-#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
+#define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
+#define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
+#define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
+#define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
+#define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
+#define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
+
+#define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
+#define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
+#define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
+#define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
+#define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
+
 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
-#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
 #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
 #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
+#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
+#define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
+#define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
+
 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
+#define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
+
+#define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
+#define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
 
-#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
+#define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
+#define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
+#define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
+#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
@@ -586,10 +447,14 @@
 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
 
+#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
+#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
+
+#define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
+#define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
+
 /* VHE encodings for architectural EL0/1 system registers */
 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
-#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
-#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
@@ -599,11 +464,9 @@
 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
-#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
-#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
@@ -612,37 +475,41 @@
 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
 
+#define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
+
 /* Common SCTLR_ELx flags. */
+#define SCTLR_ELx_ENTP2	(BIT(60))
 #define SCTLR_ELx_DSSBS	(BIT(44))
 #define SCTLR_ELx_ATA	(BIT(43))
 
-#define SCTLR_ELx_TCF_SHIFT	40
-#define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
-#define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
-#define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
-#define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
-
+#define SCTLR_ELx_EE_SHIFT	25
 #define SCTLR_ELx_ENIA_SHIFT	31
 
-#define SCTLR_ELx_ITFSB	(BIT(37))
-#define SCTLR_ELx_ENIA	(BIT(SCTLR_ELx_ENIA_SHIFT))
-#define SCTLR_ELx_ENIB	(BIT(30))
-#define SCTLR_ELx_ENDA	(BIT(27))
-#define SCTLR_ELx_EE    (BIT(25))
-#define SCTLR_ELx_IESB	(BIT(21))
-#define SCTLR_ELx_WXN	(BIT(19))
-#define SCTLR_ELx_ENDB	(BIT(13))
-#define SCTLR_ELx_I	(BIT(12))
-#define SCTLR_ELx_SA	(BIT(3))
-#define SCTLR_ELx_C	(BIT(2))
-#define SCTLR_ELx_A	(BIT(1))
-#define SCTLR_ELx_M	(BIT(0))
+#define SCTLR_ELx_ITFSB	 (BIT(37))
+#define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
+#define SCTLR_ELx_ENIB	 (BIT(30))
+#define SCTLR_ELx_LSMAOE (BIT(29))
+#define SCTLR_ELx_nTLSMD (BIT(28))
+#define SCTLR_ELx_ENDA	 (BIT(27))
+#define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
+#define SCTLR_ELx_EIS	 (BIT(22))
+#define SCTLR_ELx_IESB	 (BIT(21))
+#define SCTLR_ELx_TSCXT	 (BIT(20))
+#define SCTLR_ELx_WXN	 (BIT(19))
+#define SCTLR_ELx_ENDB	 (BIT(13))
+#define SCTLR_ELx_I	 (BIT(12))
+#define SCTLR_ELx_EOS	 (BIT(11))
+#define SCTLR_ELx_SA	 (BIT(3))
+#define SCTLR_ELx_C	 (BIT(2))
+#define SCTLR_ELx_A	 (BIT(1))
+#define SCTLR_ELx_M	 (BIT(0))
 
 /* SCTLR_EL2 specific flags. */
 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
 			 (BIT(29)))
 
+#define SCTLR_EL2_BT	(BIT(36))
 #ifdef CONFIG_CPU_BIG_ENDIAN
 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
 #else
@@ -658,33 +525,6 @@
 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
 
 /* SCTLR_EL1 specific flags. */
-#define SCTLR_EL1_EPAN		(BIT(57))
-#define SCTLR_EL1_ATA0		(BIT(42))
-
-#define SCTLR_EL1_TCF0_SHIFT	38
-#define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
-#define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
-#define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
-#define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
-
-#define SCTLR_EL1_BT1		(BIT(36))
-#define SCTLR_EL1_BT0		(BIT(35))
-#define SCTLR_EL1_UCI		(BIT(26))
-#define SCTLR_EL1_E0E		(BIT(24))
-#define SCTLR_EL1_SPAN		(BIT(23))
-#define SCTLR_EL1_NTWE		(BIT(18))
-#define SCTLR_EL1_NTWI		(BIT(16))
-#define SCTLR_EL1_UCT		(BIT(15))
-#define SCTLR_EL1_DZE		(BIT(14))
-#define SCTLR_EL1_UMA		(BIT(9))
-#define SCTLR_EL1_SED		(BIT(8))
-#define SCTLR_EL1_ITD		(BIT(7))
-#define SCTLR_EL1_CP15BEN	(BIT(5))
-#define SCTLR_EL1_SA0		(BIT(4))
-
-#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
-			 (BIT(29)))
-
 #ifdef CONFIG_CPU_BIG_ENDIAN
 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
 #else
@@ -692,14 +532,17 @@
 #endif
 
 #define INIT_SCTLR_EL1_MMU_OFF \
-	(ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
+	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
+	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
 
 #define INIT_SCTLR_EL1_MMU_ON \
-	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   | SCTLR_EL1_SA0   | \
-	 SCTLR_EL1_SED  | SCTLR_ELx_I    | SCTLR_EL1_DZE  | SCTLR_EL1_UCT   | \
-	 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
-	 SCTLR_ELx_ATA  | SCTLR_EL1_ATA0 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI   | \
-	 SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
+	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
+	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
+	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
+	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
+	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
+	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
+	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
 
 /* MAIR_ELx memory attributes (used by Linux) */
 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
@@ -712,387 +555,68 @@
 /* Position the attr at the correct index */
 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
 
-/* id_aa64isar0 */
-#define ID_AA64ISAR0_RNDR_SHIFT		60
-#define ID_AA64ISAR0_TLB_SHIFT		56
-#define ID_AA64ISAR0_TS_SHIFT		52
-#define ID_AA64ISAR0_FHM_SHIFT		48
-#define ID_AA64ISAR0_DP_SHIFT		44
-#define ID_AA64ISAR0_SM4_SHIFT		40
-#define ID_AA64ISAR0_SM3_SHIFT		36
-#define ID_AA64ISAR0_SHA3_SHIFT		32
-#define ID_AA64ISAR0_RDM_SHIFT		28
-#define ID_AA64ISAR0_ATOMICS_SHIFT	20
-#define ID_AA64ISAR0_CRC32_SHIFT	16
-#define ID_AA64ISAR0_SHA2_SHIFT		12
-#define ID_AA64ISAR0_SHA1_SHIFT		8
-#define ID_AA64ISAR0_AES_SHIFT		4
-
-#define ID_AA64ISAR0_TLB_RANGE_NI	0x0
-#define ID_AA64ISAR0_TLB_RANGE		0x2
-
-/* id_aa64isar1 */
-#define ID_AA64ISAR1_I8MM_SHIFT		52
-#define ID_AA64ISAR1_DGH_SHIFT		48
-#define ID_AA64ISAR1_BF16_SHIFT		44
-#define ID_AA64ISAR1_SPECRES_SHIFT	40
-#define ID_AA64ISAR1_SB_SHIFT		36
-#define ID_AA64ISAR1_FRINTTS_SHIFT	32
-#define ID_AA64ISAR1_GPI_SHIFT		28
-#define ID_AA64ISAR1_GPA_SHIFT		24
-#define ID_AA64ISAR1_LRCPC_SHIFT	20
-#define ID_AA64ISAR1_FCMA_SHIFT		16
-#define ID_AA64ISAR1_JSCVT_SHIFT	12
-#define ID_AA64ISAR1_API_SHIFT		8
-#define ID_AA64ISAR1_APA_SHIFT		4
-#define ID_AA64ISAR1_DPB_SHIFT		0
-
-#define ID_AA64ISAR1_APA_NI			0x0
-#define ID_AA64ISAR1_APA_ARCHITECTED		0x1
-#define ID_AA64ISAR1_APA_ARCH_EPAC		0x2
-#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5
-#define ID_AA64ISAR1_API_NI			0x0
-#define ID_AA64ISAR1_API_IMP_DEF		0x1
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5
-#define ID_AA64ISAR1_GPA_NI			0x0
-#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1
-#define ID_AA64ISAR1_GPI_NI			0x0
-#define ID_AA64ISAR1_GPI_IMP_DEF		0x1
-
 /* id_aa64pfr0 */
-#define ID_AA64PFR0_CSV3_SHIFT		60
-#define ID_AA64PFR0_CSV2_SHIFT		56
-#define ID_AA64PFR0_DIT_SHIFT		48
-#define ID_AA64PFR0_AMU_SHIFT		44
-#define ID_AA64PFR0_MPAM_SHIFT		40
-#define ID_AA64PFR0_SEL2_SHIFT		36
-#define ID_AA64PFR0_SVE_SHIFT		32
-#define ID_AA64PFR0_RAS_SHIFT		28
-#define ID_AA64PFR0_GIC_SHIFT		24
-#define ID_AA64PFR0_ASIMD_SHIFT		20
-#define ID_AA64PFR0_FP_SHIFT		16
-#define ID_AA64PFR0_EL3_SHIFT		12
-#define ID_AA64PFR0_EL2_SHIFT		8
-#define ID_AA64PFR0_EL1_SHIFT		4
-#define ID_AA64PFR0_EL0_SHIFT		0
-
-#define ID_AA64PFR0_AMU			0x1
-#define ID_AA64PFR0_SVE			0x1
-#define ID_AA64PFR0_RAS_V1		0x1
-#define ID_AA64PFR0_RAS_V1P1		0x2
-#define ID_AA64PFR0_FP_NI		0xf
-#define ID_AA64PFR0_FP_SUPPORTED	0x0
-#define ID_AA64PFR0_ASIMD_NI		0xf
-#define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
-#define ID_AA64PFR0_ELx_64BIT_ONLY	0x1
-#define ID_AA64PFR0_ELx_32BIT_64BIT	0x2
-
-/* id_aa64pfr1 */
-#define ID_AA64PFR1_MPAMFRAC_SHIFT	16
-#define ID_AA64PFR1_RASFRAC_SHIFT	12
-#define ID_AA64PFR1_MTE_SHIFT		8
-#define ID_AA64PFR1_SSBS_SHIFT		4
-#define ID_AA64PFR1_BT_SHIFT		0
-
-#define ID_AA64PFR1_SSBS_PSTATE_NI	0
-#define ID_AA64PFR1_SSBS_PSTATE_ONLY	1
-#define ID_AA64PFR1_SSBS_PSTATE_INSNS	2
-#define ID_AA64PFR1_BT_BTI		0x1
-
-#define ID_AA64PFR1_MTE_NI		0x0
-#define ID_AA64PFR1_MTE_EL0		0x1
-#define ID_AA64PFR1_MTE			0x2
-
-/* id_aa64zfr0 */
-#define ID_AA64ZFR0_F64MM_SHIFT		56
-#define ID_AA64ZFR0_F32MM_SHIFT		52
-#define ID_AA64ZFR0_I8MM_SHIFT		44
-#define ID_AA64ZFR0_SM4_SHIFT		40
-#define ID_AA64ZFR0_SHA3_SHIFT		32
-#define ID_AA64ZFR0_BF16_SHIFT		20
-#define ID_AA64ZFR0_BITPERM_SHIFT	16
-#define ID_AA64ZFR0_AES_SHIFT		4
-#define ID_AA64ZFR0_SVEVER_SHIFT	0
-
-#define ID_AA64ZFR0_F64MM		0x1
-#define ID_AA64ZFR0_F32MM		0x1
-#define ID_AA64ZFR0_I8MM		0x1
-#define ID_AA64ZFR0_BF16		0x1
-#define ID_AA64ZFR0_SM4			0x1
-#define ID_AA64ZFR0_SHA3		0x1
-#define ID_AA64ZFR0_BITPERM		0x1
-#define ID_AA64ZFR0_AES			0x1
-#define ID_AA64ZFR0_AES_PMULL		0x2
-#define ID_AA64ZFR0_SVEVER_SVE2		0x1
+#define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
+#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
 
 /* id_aa64mmfr0 */
-#define ID_AA64MMFR0_ECV_SHIFT		60
-#define ID_AA64MMFR0_FGT_SHIFT		56
-#define ID_AA64MMFR0_EXS_SHIFT		44
-#define ID_AA64MMFR0_TGRAN4_2_SHIFT	40
-#define ID_AA64MMFR0_TGRAN64_2_SHIFT	36
-#define ID_AA64MMFR0_TGRAN16_2_SHIFT	32
-#define ID_AA64MMFR0_TGRAN4_SHIFT	28
-#define ID_AA64MMFR0_TGRAN64_SHIFT	24
-#define ID_AA64MMFR0_TGRAN16_SHIFT	20
-#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
-#define ID_AA64MMFR0_SNSMEM_SHIFT	12
-#define ID_AA64MMFR0_BIGENDEL_SHIFT	8
-#define ID_AA64MMFR0_ASID_SHIFT		4
-#define ID_AA64MMFR0_PARANGE_SHIFT	0
-
-#define ID_AA64MMFR0_ASID_8		0x0
-#define ID_AA64MMFR0_ASID_16		0x2
-
-#define ID_AA64MMFR0_TGRAN4_NI			0xf
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7
-#define ID_AA64MMFR0_TGRAN64_NI			0xf
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7
-#define ID_AA64MMFR0_TGRAN16_NI			0x0
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf
-
-#define ID_AA64MMFR0_PARANGE_32		0x0
-#define ID_AA64MMFR0_PARANGE_36		0x1
-#define ID_AA64MMFR0_PARANGE_40		0x2
-#define ID_AA64MMFR0_PARANGE_42		0x3
-#define ID_AA64MMFR0_PARANGE_44		0x4
-#define ID_AA64MMFR0_PARANGE_48		0x5
-#define ID_AA64MMFR0_PARANGE_52		0x6
+#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
+#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
+#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
+#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
+#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
+#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
 
 #define ARM64_MIN_PARANGE_BITS		32
 
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
 
 #ifdef CONFIG_ARM64_PA_BITS_52
-#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52
+#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
 #else
-#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
+#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-/* id_aa64mmfr1 */
-#define ID_AA64MMFR1_ETS_SHIFT		36
-#define ID_AA64MMFR1_TWED_SHIFT		32
-#define ID_AA64MMFR1_XNX_SHIFT		28
-#define ID_AA64MMFR1_SPECSEI_SHIFT	24
-#define ID_AA64MMFR1_PAN_SHIFT		20
-#define ID_AA64MMFR1_LOR_SHIFT		16
-#define ID_AA64MMFR1_HPD_SHIFT		12
-#define ID_AA64MMFR1_VHE_SHIFT		8
-#define ID_AA64MMFR1_VMIDBITS_SHIFT	4
-#define ID_AA64MMFR1_HADBS_SHIFT	0
-
-#define ID_AA64MMFR1_VMIDBITS_8		0
-#define ID_AA64MMFR1_VMIDBITS_16	2
-
-/* id_aa64mmfr2 */
-#define ID_AA64MMFR2_E0PD_SHIFT		60
-#define ID_AA64MMFR2_EVT_SHIFT		56
-#define ID_AA64MMFR2_BBM_SHIFT		52
-#define ID_AA64MMFR2_TTL_SHIFT		48
-#define ID_AA64MMFR2_FWB_SHIFT		40
-#define ID_AA64MMFR2_IDS_SHIFT		36
-#define ID_AA64MMFR2_AT_SHIFT		32
-#define ID_AA64MMFR2_ST_SHIFT		28
-#define ID_AA64MMFR2_NV_SHIFT		24
-#define ID_AA64MMFR2_CCIDX_SHIFT	20
-#define ID_AA64MMFR2_LVA_SHIFT		16
-#define ID_AA64MMFR2_IESB_SHIFT		12
-#define ID_AA64MMFR2_LSM_SHIFT		8
-#define ID_AA64MMFR2_UAO_SHIFT		4
-#define ID_AA64MMFR2_CNP_SHIFT		0
-
-/* id_aa64dfr0 */
-#define ID_AA64DFR0_MTPMU_SHIFT		48
-#define ID_AA64DFR0_TRBE_SHIFT		44
-#define ID_AA64DFR0_TRACE_FILT_SHIFT	40
-#define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
-#define ID_AA64DFR0_PMSVER_SHIFT	32
-#define ID_AA64DFR0_CTX_CMPS_SHIFT	28
-#define ID_AA64DFR0_WRPS_SHIFT		20
-#define ID_AA64DFR0_BRPS_SHIFT		12
-#define ID_AA64DFR0_PMUVER_SHIFT	8
-#define ID_AA64DFR0_TRACEVER_SHIFT	4
-#define ID_AA64DFR0_DEBUGVER_SHIFT	0
-
-#define ID_AA64DFR0_PMUVER_8_0		0x1
-#define ID_AA64DFR0_PMUVER_8_1		0x4
-#define ID_AA64DFR0_PMUVER_8_4		0x5
-#define ID_AA64DFR0_PMUVER_8_5		0x6
-#define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
-
-#define ID_AA64DFR0_PMSVER_8_2		0x1
-#define ID_AA64DFR0_PMSVER_8_3		0x2
-
-#define ID_DFR0_PERFMON_SHIFT		24
-
-#define ID_DFR0_PERFMON_8_0		0x3
-#define ID_DFR0_PERFMON_8_1		0x4
-#define ID_DFR0_PERFMON_8_4		0x5
-#define ID_DFR0_PERFMON_8_5		0x6
-
-#define ID_ISAR4_SWP_FRAC_SHIFT		28
-#define ID_ISAR4_PSR_M_SHIFT		24
-#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT	20
-#define ID_ISAR4_BARRIER_SHIFT		16
-#define ID_ISAR4_SMC_SHIFT		12
-#define ID_ISAR4_WRITEBACK_SHIFT	8
-#define ID_ISAR4_WITHSHIFTS_SHIFT	4
-#define ID_ISAR4_UNPRIV_SHIFT		0
-
-#define ID_DFR1_MTPMU_SHIFT		0
-
-#define ID_ISAR0_DIVIDE_SHIFT		24
-#define ID_ISAR0_DEBUG_SHIFT		20
-#define ID_ISAR0_COPROC_SHIFT		16
-#define ID_ISAR0_CMPBRANCH_SHIFT	12
-#define ID_ISAR0_BITFIELD_SHIFT		8
-#define ID_ISAR0_BITCOUNT_SHIFT		4
-#define ID_ISAR0_SWAP_SHIFT		0
-
-#define ID_ISAR5_RDM_SHIFT		24
-#define ID_ISAR5_CRC32_SHIFT		16
-#define ID_ISAR5_SHA2_SHIFT		12
-#define ID_ISAR5_SHA1_SHIFT		8
-#define ID_ISAR5_AES_SHIFT		4
-#define ID_ISAR5_SEVL_SHIFT		0
-
-#define ID_ISAR6_I8MM_SHIFT		24
-#define ID_ISAR6_BF16_SHIFT		20
-#define ID_ISAR6_SPECRES_SHIFT		16
-#define ID_ISAR6_SB_SHIFT		12
-#define ID_ISAR6_FHM_SHIFT		8
-#define ID_ISAR6_DP_SHIFT		4
-#define ID_ISAR6_JSCVT_SHIFT		0
-
-#define ID_MMFR0_INNERSHR_SHIFT		28
-#define ID_MMFR0_FCSE_SHIFT		24
-#define ID_MMFR0_AUXREG_SHIFT		20
-#define ID_MMFR0_TCM_SHIFT		16
-#define ID_MMFR0_SHARELVL_SHIFT		12
-#define ID_MMFR0_OUTERSHR_SHIFT		8
-#define ID_MMFR0_PMSA_SHIFT		4
-#define ID_MMFR0_VMSA_SHIFT		0
-
-#define ID_MMFR4_EVT_SHIFT		28
-#define ID_MMFR4_CCIDX_SHIFT		24
-#define ID_MMFR4_LSM_SHIFT		20
-#define ID_MMFR4_HPDS_SHIFT		16
-#define ID_MMFR4_CNP_SHIFT		12
-#define ID_MMFR4_XNX_SHIFT		8
-#define ID_MMFR4_AC2_SHIFT		4
-#define ID_MMFR4_SPECSEI_SHIFT		0
-
-#define ID_MMFR5_ETS_SHIFT		0
-
-#define ID_PFR0_DIT_SHIFT		24
-#define ID_PFR0_CSV2_SHIFT		16
-#define ID_PFR0_STATE3_SHIFT		12
-#define ID_PFR0_STATE2_SHIFT		8
-#define ID_PFR0_STATE1_SHIFT		4
-#define ID_PFR0_STATE0_SHIFT		0
-
-#define ID_DFR0_PERFMON_SHIFT		24
-#define ID_DFR0_MPROFDBG_SHIFT		20
-#define ID_DFR0_MMAPTRC_SHIFT		16
-#define ID_DFR0_COPTRC_SHIFT		12
-#define ID_DFR0_MMAPDBG_SHIFT		8
-#define ID_DFR0_COPSDBG_SHIFT		4
-#define ID_DFR0_COPDBG_SHIFT		0
-
-#define ID_PFR2_SSBS_SHIFT		4
-#define ID_PFR2_CSV3_SHIFT		0
-
-#define MVFR0_FPROUND_SHIFT		28
-#define MVFR0_FPSHVEC_SHIFT		24
-#define MVFR0_FPSQRT_SHIFT		20
-#define MVFR0_FPDIVIDE_SHIFT		16
-#define MVFR0_FPTRAP_SHIFT		12
-#define MVFR0_FPDP_SHIFT		8
-#define MVFR0_FPSP_SHIFT		4
-#define MVFR0_SIMD_SHIFT		0
-
-#define MVFR1_SIMDFMAC_SHIFT		28
-#define MVFR1_FPHP_SHIFT		24
-#define MVFR1_SIMDHP_SHIFT		20
-#define MVFR1_SIMDSP_SHIFT		16
-#define MVFR1_SIMDINT_SHIFT		12
-#define MVFR1_SIMDLS_SHIFT		8
-#define MVFR1_FPDNAN_SHIFT		4
-#define MVFR1_FPFTZ_SHIFT		0
-
-#define ID_PFR1_GIC_SHIFT		28
-#define ID_PFR1_VIRT_FRAC_SHIFT		24
-#define ID_PFR1_SEC_FRAC_SHIFT		20
-#define ID_PFR1_GENTIMER_SHIFT		16
-#define ID_PFR1_VIRTUALIZATION_SHIFT	12
-#define ID_PFR1_MPROGMOD_SHIFT		8
-#define ID_PFR1_SECURITY_SHIFT		4
-#define ID_PFR1_PROGMOD_SHIFT		0
-
 #if defined(CONFIG_ARM64_4K_PAGES)
-#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
-#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN4_2_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
+#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
 #elif defined(CONFIG_ARM64_16K_PAGES)
-#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
-#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN16_2_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
+#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
 #elif defined(CONFIG_ARM64_64K_PAGES)
-#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
-#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN64_2_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
+#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
 #endif
 
-#define MVFR2_FPMISC_SHIFT		4
-#define MVFR2_SIMDMISC_SHIFT		0
-
-#define DCZID_DZP_SHIFT			4
-#define DCZID_BS_SHIFT			0
+#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
+#define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
 
-/*
- * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
- * are reserved by the SVE architecture for future expansion of the LEN
- * field, with compatible semantics.
- */
-#define ZCR_ELx_LEN_SHIFT	0
-#define ZCR_ELx_LEN_SIZE	9
-#define ZCR_ELx_LEN_MASK	0x1ff
+#define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
+#define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
 
 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
-#define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
-
-/* TCR EL1 Bit Definitions */
-#define SYS_TCR_EL1_TCMA1	(BIT(58))
-#define SYS_TCR_EL1_TCMA0	(BIT(57))
 
 /* GCR_EL1 Definitions */
 #define SYS_GCR_EL1_RRND	(BIT(16))
 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
 
+#define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
+
 /* RGSR_EL1 Definitions */
 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
 #define SYS_RGSR_EL1_SEED_SHIFT	8
 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
 
-/* GMID_EL1 field definitions */
-#define SYS_GMID_EL1_BS_SHIFT	0
-#define SYS_GMID_EL1_BS_SIZE	4
-
 /* TFSR{,E0}_EL1 bit definitions */
 #define SYS_TFSR_EL1_TF0_SHIFT	0
 #define SYS_TFSR_EL1_TF1_SHIFT	1
@@ -1103,6 +627,7 @@
 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
 
 #define TRFCR_ELx_TS_SHIFT		5
+#define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
 #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
 #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
 #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
@@ -1110,7 +635,6 @@
 #define TRFCR_ELx_ExTRE			BIT(1)
 #define TRFCR_ELx_E0TRE			BIT(0)
 
-
 /* GIC Hypervisor interface registers */
 /* ICH_MISR_EL2 bit definitions */
 #define ICH_MISR_EOI		(1 << 0)
@@ -1137,6 +661,7 @@
 #define ICH_HCR_TC		(1 << 10)
 #define ICH_HCR_TALL0		(1 << 11)
 #define ICH_HCR_TALL1		(1 << 12)
+#define ICH_HCR_TDIR		(1 << 14)
 #define ICH_HCR_EOIcount_SHIFT	27
 #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
 
@@ -1169,49 +694,60 @@
 #define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
 #define ICH_VTR_A3V_SHIFT	21
 #define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
+#define ICH_VTR_TDS_SHIFT	19
+#define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
+
+/*
+ * Permission Indirection Extension (PIE) permission encodings.
+ * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
+ */
+#define PIE_NONE_O	0x0
+#define PIE_R_O		0x1
+#define PIE_X_O		0x2
+#define PIE_RX_O	0x3
+#define PIE_RW_O	0x5
+#define PIE_RWnX_O	0x6
+#define PIE_RWX_O	0x7
+#define PIE_R		0x8
+#define PIE_GCS		0x9
+#define PIE_RX		0xa
+#define PIE_RW		0xc
+#define PIE_RWX		0xe
+
+#define PIRx_ELx_PERM(idx, perm)	((perm) << ((idx) * 4))
 
 #define ARM64_FEATURE_FIELD_BITS	4
 
-/* Create a mask for the feature bits of the specified feature. */
-#define ARM64_FEATURE_MASK(x)	(GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
+/* Defined for compatibility only, do not add new users. */
+#define ARM64_FEATURE_MASK(x)	(x##_MASK)
 
 #ifdef __ASSEMBLY__
 
-	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
-	.equ	.L__reg_num_x\num, \num
-	.endr
-	.equ	.L__reg_num_xzr, 31
-
 	.macro	mrs_s, rt, sreg
-	 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
+	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
 	.endm
 
 	.macro	msr_s, sreg, rt
-	__emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
+	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
 	.endm
 
 #else
 
+#include <linux/bitfield.h>
 #include <linux/build_bug.h>
 #include <linux/types.h>
 #include <asm/alternative.h>
 
-#define __DEFINE_MRS_MSR_S_REGNUM				\
-"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
-"	.equ	.L__reg_num_x\\num, \\num\n"			\
-"	.endr\n"						\
-"	.equ	.L__reg_num_xzr, 31\n"
-
 #define DEFINE_MRS_S						\
-	__DEFINE_MRS_MSR_S_REGNUM				\
+	__DEFINE_ASM_GPR_NUMS					\
 "	.macro	mrs_s, rt, sreg\n"				\
-	__emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))	\
+	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
 "	.endm\n"
 
 #define DEFINE_MSR_S						\
-	__DEFINE_MRS_MSR_S_REGNUM				\
+	__DEFINE_ASM_GPR_NUMS					\
 "	.macro	msr_s, sreg, rt\n"				\
-	__emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))	\
+	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
 "	.endm\n"
 
 #define UNDEFINE_MRS_S						\
@@ -1291,6 +827,15 @@
 	par;								\
 })
 
+#define SYS_FIELD_GET(reg, field, val)		\
+		 FIELD_GET(reg##_##field##_MASK, val)
+
+#define SYS_FIELD_PREP(reg, field, val)		\
+		 FIELD_PREP(reg##_##field##_MASK, val)
+
+#define SYS_FIELD_PREP_ENUM(reg, field, val)		\
+		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
+
 #endif
 
 #endif	/* __ASM_SYSREG_H */
diff --git a/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c b/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
index b90580840b22..8e5bd07a3727 100644
--- a/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
+++ b/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
@@ -146,8 +146,8 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu)
 
 	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
 
-	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL0), val);
-	return el0 == ID_AA64PFR0_ELx_64BIT_ONLY;
+	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
+	return el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY;
 }
 
 int main(void)
diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
index f5b6cb3a0019..866002917441 100644
--- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
+++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
@@ -116,12 +116,12 @@ static void reset_debug_state(void)
 
 	/* Reset all bcr/bvr/wcr/wvr registers */
 	dfr0 = read_sysreg(id_aa64dfr0_el1);
-	brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), dfr0);
+	brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), dfr0);
 	for (i = 0; i <= brps; i++) {
 		write_dbgbcr(i, 0);
 		write_dbgbvr(i, 0);
 	}
-	wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), dfr0);
+	wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), dfr0);
 	for (i = 0; i <= wrps; i++) {
 		write_dbgwcr(i, 0);
 		write_dbgwvr(i, 0);
@@ -418,7 +418,7 @@ static void guest_code_ss(int test_cnt)
 
 static int debug_version(uint64_t id_aa64dfr0)
 {
-	return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), id_aa64dfr0);
+	return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), id_aa64dfr0);
 }
 
 static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)
@@ -539,14 +539,14 @@ void test_guest_debug_exceptions_all(uint64_t aa64dfr0)
 	int b, w, c;
 
 	/* Number of breakpoints */
-	brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), aa64dfr0) + 1;
+	brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), aa64dfr0) + 1;
 	__TEST_REQUIRE(brp_num >= 2, "At least two breakpoints are required");
 
 	/* Number of watchpoints */
-	wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), aa64dfr0) + 1;
+	wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), aa64dfr0) + 1;
 
 	/* Number of context aware breakpoints */
-	ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_CTX_CMPS), aa64dfr0) + 1;
+	ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), aa64dfr0) + 1;
 
 	pr_debug("%s brp_num:%d, wrp_num:%d, ctx_brp_num:%d\n", __func__,
 		 brp_num, wrp_num, ctx_brp_num);
diff --git a/tools/testing/selftests/kvm/aarch64/page_fault_test.c b/tools/testing/selftests/kvm/aarch64/page_fault_test.c
index 47bb914ab2fa..975d28be3cca 100644
--- a/tools/testing/selftests/kvm/aarch64/page_fault_test.c
+++ b/tools/testing/selftests/kvm/aarch64/page_fault_test.c
@@ -96,14 +96,14 @@ static bool guest_check_lse(void)
 	uint64_t isar0 = read_sysreg(id_aa64isar0_el1);
 	uint64_t atomic;
 
-	atomic = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS), isar0);
+	atomic = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC), isar0);
 	return atomic >= 2;
 }
 
 static bool guest_check_dc_zva(void)
 {
 	uint64_t dczid = read_sysreg(dczid_el0);
-	uint64_t dzp = FIELD_GET(ARM64_FEATURE_MASK(DCZID_DZP), dczid);
+	uint64_t dzp = FIELD_GET(ARM64_FEATURE_MASK(DCZID_EL0_DZP), dczid);
 
 	return dzp == 0;
 }
@@ -196,7 +196,7 @@ static bool guest_set_ha(void)
 	uint64_t hadbs, tcr;
 
 	/* Skip if HA is not supported. */
-	hadbs = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_HADBS), mmfr1);
+	hadbs = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS), mmfr1);
 	if (hadbs == 0)
 		return false;
 
diff --git a/tools/testing/selftests/kvm/lib/aarch64/processor.c b/tools/testing/selftests/kvm/lib/aarch64/processor.c
index 3a0259e25335..6fe12e985ba5 100644
--- a/tools/testing/selftests/kvm/lib/aarch64/processor.c
+++ b/tools/testing/selftests/kvm/lib/aarch64/processor.c
@@ -518,9 +518,9 @@ void aarch64_get_supported_page_sizes(uint32_t ipa,
 	err = ioctl(vcpu_fd, KVM_GET_ONE_REG, &reg);
 	TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));
 
-	*ps4k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4), val) != 0xf;
-	*ps64k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64), val) == 0;
-	*ps16k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN16), val) != 0;
+	*ps4k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN4), val) != 0xf;
+	*ps64k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN64), val) == 0;
+	*ps16k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN16), val) != 0;
 
 	close(vcpu_fd);
 	close(vm_fd);
-- 
2.42.0.609.gbb76f46606-goog


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Re: [PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Eric Auger]

Hi Oliver,

On 10/11/23 21:57, Oliver Upton wrote:
> From: Jing Zhang <jingzhangos@google.com>
> 
> The users of sysreg.h (perf, KVM selftests) are now generating the
> necessary sysreg-defs.h; sync sysreg.h with the kernel sources and
> fix the KVM selftests that use macros which suffered a rename.
> 
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  tools/arch/arm64/include/asm/gpr-num.h        |  26 +
>  tools/arch/arm64/include/asm/sysreg.h         | 839 ++++--------------
>  .../selftests/kvm/aarch64/aarch32_id_regs.c   |   4 +-
>  .../selftests/kvm/aarch64/debug-exceptions.c  |  12 +-
>  .../selftests/kvm/aarch64/page_fault_test.c   |   6 +-
>  .../selftests/kvm/lib/aarch64/processor.c     |   6 +-
>  6 files changed, 232 insertions(+), 661 deletions(-)
>  create mode 100644 tools/arch/arm64/include/asm/gpr-num.h
> 
> diff --git a/tools/arch/arm64/include/asm/gpr-num.h b/tools/arch/arm64/include/asm/gpr-num.h
> new file mode 100644
> index 000000000000..05da4a7c5788
> --- /dev/null
> +++ b/tools/arch/arm64/include/asm/gpr-num.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef __ASM_GPR_NUM_H
> +#define __ASM_GPR_NUM_H
> +
> +#ifdef __ASSEMBLY__
> +
> +	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> +	.equ	.L__gpr_num_x\num, \num
> +	.equ	.L__gpr_num_w\num, \num
> +	.endr
> +	.equ	.L__gpr_num_xzr, 31
> +	.equ	.L__gpr_num_wzr, 31
> +
> +#else /* __ASSEMBLY__ */
> +
> +#define __DEFINE_ASM_GPR_NUMS					\
> +"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
> +"	.equ	.L__gpr_num_x\\num, \\num\n"			\
> +"	.equ	.L__gpr_num_w\\num, \\num\n"			\
> +"	.endr\n"						\
> +"	.equ	.L__gpr_num_xzr, 31\n"				\
> +"	.equ	.L__gpr_num_wzr, 31\n"
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* __ASM_GPR_NUM_H */
> diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
> index 7640fa27be94..ccc13e991376 100644
> --- a/tools/arch/arm64/include/asm/sysreg.h
> +++ b/tools/arch/arm64/include/asm/sysreg.h
> @@ -12,6 +12,8 @@
>  #include <linux/bits.h>
>  #include <linux/stringify.h>
>  
> +#include <asm/gpr-num.h>
> +
>  /*
>   * ARMv8 ARM reserves the following encoding for system registers:
>   * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
> @@ -87,20 +89,24 @@
>   */
>  #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
>  #define PSTATE_Imm_shift		CRm_shift
> +#define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
>  
>  #define PSTATE_PAN			pstate_field(0, 4)
>  #define PSTATE_UAO			pstate_field(0, 3)
>  #define PSTATE_SSBS			pstate_field(3, 1)
> +#define PSTATE_DIT			pstate_field(3, 2)
>  #define PSTATE_TCO			pstate_field(3, 4)
>  
> -#define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
> -#define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
> -#define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
> -#define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
> +#define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
> +#define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
> +#define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
> +#define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
> +#define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
>  
>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>  #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
> +#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
could you comment on the *DIT* addictions, what is it for?
>  
>  #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
>  	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
> @@ -108,25 +114,43 @@
>  #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
>  
>  #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
> +#define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
> +#define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
>  #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
> +#define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
> +#define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
>  #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
> +#define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
> +#define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
also the above additions are not really documented in the commit msg,
what is it for?
> +
> +/*
> + * Automatically generated definitions for system registers, the
> + * manual encodings below are in the process of being converted to
> + * come from here. The header relies on the definition of sys_reg()
> + * earlier in this file.
> + */
> +#include "asm/sysreg-defs.h"
strange to have this include in the middle of the file
>  
>  /*
>   * System registers, organised loosely by encoding but grouped together
>   * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
>   */
> -#define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
> -#define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
> -#define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
> -#define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
> -#define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
> +#define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
> +#define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
> +#define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
This is pretty difficult to review. I originally expected mostly
removals of definitions now included in asm/sysreg-defs.h and a few
renamings but there are plenty of changes. Wouldn't it possible to split
the patch into smaller patches including first removals and then
incremental steps for renamings/additions?

Thanks

Eric
> +
>  #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
>  #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
>  #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
>  #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
>  #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
> -#define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
> +
>  #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
> +#define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
> +#define OSLSR_EL1_OSLM_NI		0
> +#define OSLSR_EL1_OSLM_IMPLEMENTED	BIT(3)
> +#define OSLSR_EL1_OSLK			BIT(1)
> +
>  #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
>  #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
>  #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
> @@ -142,59 +166,12 @@
>  #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
>  #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
>  
> -#define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
> -#define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
> -#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
> -#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
> -#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
> -#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
> -#define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
> -#define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
> -#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
> -#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
> -#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
> -#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)
> -
> -#define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
> -#define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
> -#define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
> -#define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
> -#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
> -#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
> -#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
> -
> -#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
> -#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
> -#define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
> -
> -#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
> -#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
> -#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
> -
> -#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
> -#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
> -
> -#define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
> -#define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
> -
> -#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
> -#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
> -
> -#define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
> -#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
> -#define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
> -
> -#define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
>  #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
> -#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
>  #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
>  #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
>  
> -#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
>  #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
>  
> -#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
> -#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
>  #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
>  
>  #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
> @@ -230,159 +207,33 @@
>  #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
>  #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
>  
> -#define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
>  #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
>  
>  #define SYS_PAR_EL1_F			BIT(0)
>  #define SYS_PAR_EL1_FST			GENMASK(6, 1)
>  
>  /*** Statistical Profiling Extension ***/
> -/* ID registers */
> -#define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)
> -#define SYS_PMSIDR_EL1_FE_SHIFT		0
> -#define SYS_PMSIDR_EL1_FT_SHIFT		1
> -#define SYS_PMSIDR_EL1_FL_SHIFT		2
> -#define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3
> -#define SYS_PMSIDR_EL1_LDS_SHIFT	4
> -#define SYS_PMSIDR_EL1_ERND_SHIFT	5
> -#define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8
> -#define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL
> -#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
> -#define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL
> -#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16
> -#define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL
> -
> -#define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)
> -#define SYS_PMBIDR_EL1_ALIGN_SHIFT	0
> -#define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU
> -#define SYS_PMBIDR_EL1_P_SHIFT		4
> -#define SYS_PMBIDR_EL1_F_SHIFT		5
> -
> -/* Sampling controls */
> -#define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)
> -#define SYS_PMSCR_EL1_E0SPE_SHIFT	0
> -#define SYS_PMSCR_EL1_E1SPE_SHIFT	1
> -#define SYS_PMSCR_EL1_CX_SHIFT		3
> -#define SYS_PMSCR_EL1_PA_SHIFT		4
> -#define SYS_PMSCR_EL1_TS_SHIFT		5
> -#define SYS_PMSCR_EL1_PCT_SHIFT		6
> -
> -#define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)
> -#define SYS_PMSCR_EL2_E0HSPE_SHIFT	0
> -#define SYS_PMSCR_EL2_E2SPE_SHIFT	1
> -#define SYS_PMSCR_EL2_CX_SHIFT		3
> -#define SYS_PMSCR_EL2_PA_SHIFT		4
> -#define SYS_PMSCR_EL2_TS_SHIFT		5
> -#define SYS_PMSCR_EL2_PCT_SHIFT		6
> -
> -#define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)
> -
> -#define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)
> -#define SYS_PMSIRR_EL1_RND_SHIFT	0
> -#define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8
> -#define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL
> -
> -/* Filtering controls */
> -#define SYS_PMSNEVFR_EL1		sys_reg(3, 0, 9, 9, 1)
> -
> -#define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)
> -#define SYS_PMSFCR_EL1_FE_SHIFT		0
> -#define SYS_PMSFCR_EL1_FT_SHIFT		1
> -#define SYS_PMSFCR_EL1_FL_SHIFT		2
> -#define SYS_PMSFCR_EL1_B_SHIFT		16
> -#define SYS_PMSFCR_EL1_LD_SHIFT		17
> -#define SYS_PMSFCR_EL1_ST_SHIFT		18
> -
> -#define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
> -#define SYS_PMSEVFR_EL1_RES0_8_2	\
> +#define PMSEVFR_EL1_RES0_IMP	\
>  	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
>  	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
> -#define SYS_PMSEVFR_EL1_RES0_8_3	\
> -	(SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
> -
> -#define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
> -#define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
> -
> -/* Buffer controls */
> -#define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)
> -#define SYS_PMBLIMITR_EL1_E_SHIFT	0
> -#define SYS_PMBLIMITR_EL1_FM_SHIFT	1
> -#define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL
> -#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
> -
> -#define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)
> +#define PMSEVFR_EL1_RES0_V1P1	\
> +	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
> +#define PMSEVFR_EL1_RES0_V1P2	\
> +	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
>  
>  /* Buffer error reporting */
> -#define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)
> -#define SYS_PMBSR_EL1_COLL_SHIFT	16
> -#define SYS_PMBSR_EL1_S_SHIFT		17
> -#define SYS_PMBSR_EL1_EA_SHIFT		18
> -#define SYS_PMBSR_EL1_DL_SHIFT		19
> -#define SYS_PMBSR_EL1_EC_SHIFT		26
> -#define SYS_PMBSR_EL1_EC_MASK		0x3fUL
> -
> -#define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
> -#define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
> -#define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
> -
> -#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0
> -#define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL
> +#define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
> +#define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
>  
> -#define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0
> -#define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL
> +#define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
> +#define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
>  
> -#define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
> +#define PMBSR_EL1_BUF_BSC_FULL		0x1UL
>  
>  /*** End of Statistical Profiling Extension ***/
>  
> -/*
> - * TRBE Registers
> - */
> -#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
> -#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
> -#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
> -#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
> -#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
> -#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
> -#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
> -
> -#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
> -#define TRBLIMITR_LIMIT_SHIFT		12
> -#define TRBLIMITR_NVM			BIT(5)
> -#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
> -#define TRBLIMITR_TRIG_MODE_SHIFT	3
> -#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
> -#define TRBLIMITR_FILL_MODE_SHIFT	1
> -#define TRBLIMITR_ENABLE		BIT(0)
> -#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
> -#define TRBPTR_PTR_SHIFT		0
> -#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
> -#define TRBBASER_BASE_SHIFT		12
> -#define TRBSR_EC_MASK			GENMASK(5, 0)
> -#define TRBSR_EC_SHIFT			26
> -#define TRBSR_IRQ			BIT(22)
> -#define TRBSR_TRG			BIT(21)
> -#define TRBSR_WRAP			BIT(20)
> -#define TRBSR_ABORT			BIT(18)
> -#define TRBSR_STOP			BIT(17)
> -#define TRBSR_MSS_MASK			GENMASK(15, 0)
> -#define TRBSR_MSS_SHIFT			0
> -#define TRBSR_BSC_MASK			GENMASK(5, 0)
> -#define TRBSR_BSC_SHIFT			0
> -#define TRBSR_FSC_MASK			GENMASK(5, 0)
> -#define TRBSR_FSC_SHIFT			0
> -#define TRBMAR_SHARE_MASK		GENMASK(1, 0)
> -#define TRBMAR_SHARE_SHIFT		8
> -#define TRBMAR_OUTER_MASK		GENMASK(3, 0)
> -#define TRBMAR_OUTER_SHIFT		4
> -#define TRBMAR_INNER_MASK		GENMASK(3, 0)
> -#define TRBMAR_INNER_SHIFT		0
> -#define TRBTRG_TRG_MASK			GENMASK(31, 0)
> -#define TRBTRG_TRG_SHIFT		0
> -#define TRBIDR_FLAG			BIT(5)
> -#define TRBIDR_PROG			BIT(4)
> -#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
> -#define TRBIDR_ALIGN_SHIFT		0
> +#define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
> +#define TRBSR_EL1_BSC_SHIFT		0
>  
>  #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
>  #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
> @@ -392,12 +243,6 @@
>  #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
>  #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
>  
> -#define SYS_LORSA_EL1			sys_reg(3, 0, 10, 4, 0)
> -#define SYS_LOREA_EL1			sys_reg(3, 0, 10, 4, 1)
> -#define SYS_LORN_EL1			sys_reg(3, 0, 10, 4, 2)
> -#define SYS_LORC_EL1			sys_reg(3, 0, 10, 4, 3)
> -#define SYS_LORID_EL1			sys_reg(3, 0, 10, 4, 7)
> -
>  #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
>  #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
>  
> @@ -429,23 +274,10 @@
>  #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
>  #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
>  
> -#define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
> -#define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
> -
> -#define SYS_SCXTNUM_EL1			sys_reg(3, 0, 13, 0, 7)
> -
>  #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
>  
> -#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
> -#define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
> -#define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
>  #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
>  
> -#define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
> -
> -#define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
> -#define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
> -
>  #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
>  #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
>  
> @@ -465,6 +297,7 @@
>  
>  #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
>  #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
> +#define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
>  
>  #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
>  
> @@ -506,6 +339,10 @@
>  
>  #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
>  
> +#define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
> +#define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
> +#define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
> +
>  #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
>  #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
>  #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
> @@ -515,7 +352,9 @@
>  
>  #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
>  #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
> +#define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
>  #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
> +#define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
>  
>  #define __PMEV_op2(n)			((n) & 0x7)
>  #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
> @@ -525,26 +364,48 @@
>  
>  #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
>  
> +#define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
> +#define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
> +
>  #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
> -#define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
> -#define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
> -#define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
> -#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
> +#define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
> +#define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
> +#define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
> +#define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
> +#define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
> +#define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
> +
> +#define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
> +#define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
> +#define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
> +#define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
> +#define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
> +
>  #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
> -#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
>  #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
>  #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
>  #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
>  #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
>  #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
> +#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
>  #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
> +#define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
> +#define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
>  #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
>  #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
>  #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
>  #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
> +
>  #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
> +#define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
> +
> +#define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
> +#define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
>  
> -#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
> +#define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
> +#define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
> +#define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
> +#define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
>  #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
>  #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
>  #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
> @@ -586,10 +447,14 @@
>  #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
>  #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
>  
> +#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
> +#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
> +
> +#define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
> +#define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
> +
>  /* VHE encodings for architectural EL0/1 system registers */
>  #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
> -#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
> -#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
>  #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
>  #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
>  #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
> @@ -599,11 +464,9 @@
>  #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
>  #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
>  #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
> -#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
>  #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
>  #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
>  #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
> -#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
>  #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
>  #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
>  #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
> @@ -612,37 +475,41 @@
>  #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
>  #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
>  
> +#define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
> +
>  /* Common SCTLR_ELx flags. */
> +#define SCTLR_ELx_ENTP2	(BIT(60))
>  #define SCTLR_ELx_DSSBS	(BIT(44))
>  #define SCTLR_ELx_ATA	(BIT(43))
>  
> -#define SCTLR_ELx_TCF_SHIFT	40
> -#define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
> -#define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
> -#define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
> -#define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
> -
> +#define SCTLR_ELx_EE_SHIFT	25
>  #define SCTLR_ELx_ENIA_SHIFT	31
>  
> -#define SCTLR_ELx_ITFSB	(BIT(37))
> -#define SCTLR_ELx_ENIA	(BIT(SCTLR_ELx_ENIA_SHIFT))
> -#define SCTLR_ELx_ENIB	(BIT(30))
> -#define SCTLR_ELx_ENDA	(BIT(27))
> -#define SCTLR_ELx_EE    (BIT(25))
> -#define SCTLR_ELx_IESB	(BIT(21))
> -#define SCTLR_ELx_WXN	(BIT(19))
> -#define SCTLR_ELx_ENDB	(BIT(13))
> -#define SCTLR_ELx_I	(BIT(12))
> -#define SCTLR_ELx_SA	(BIT(3))
> -#define SCTLR_ELx_C	(BIT(2))
> -#define SCTLR_ELx_A	(BIT(1))
> -#define SCTLR_ELx_M	(BIT(0))
> +#define SCTLR_ELx_ITFSB	 (BIT(37))
> +#define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
> +#define SCTLR_ELx_ENIB	 (BIT(30))
> +#define SCTLR_ELx_LSMAOE (BIT(29))
> +#define SCTLR_ELx_nTLSMD (BIT(28))
> +#define SCTLR_ELx_ENDA	 (BIT(27))
> +#define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
> +#define SCTLR_ELx_EIS	 (BIT(22))
> +#define SCTLR_ELx_IESB	 (BIT(21))
> +#define SCTLR_ELx_TSCXT	 (BIT(20))
> +#define SCTLR_ELx_WXN	 (BIT(19))
> +#define SCTLR_ELx_ENDB	 (BIT(13))
> +#define SCTLR_ELx_I	 (BIT(12))
> +#define SCTLR_ELx_EOS	 (BIT(11))
> +#define SCTLR_ELx_SA	 (BIT(3))
> +#define SCTLR_ELx_C	 (BIT(2))
> +#define SCTLR_ELx_A	 (BIT(1))
> +#define SCTLR_ELx_M	 (BIT(0))
>  
>  /* SCTLR_EL2 specific flags. */
>  #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
>  			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
>  			 (BIT(29)))
>  
> +#define SCTLR_EL2_BT	(BIT(36))
>  #ifdef CONFIG_CPU_BIG_ENDIAN
>  #define ENDIAN_SET_EL2		SCTLR_ELx_EE
>  #else
> @@ -658,33 +525,6 @@
>  	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
>  
>  /* SCTLR_EL1 specific flags. */
> -#define SCTLR_EL1_EPAN		(BIT(57))
> -#define SCTLR_EL1_ATA0		(BIT(42))
> -
> -#define SCTLR_EL1_TCF0_SHIFT	38
> -#define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
> -#define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
> -#define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
> -#define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
> -
> -#define SCTLR_EL1_BT1		(BIT(36))
> -#define SCTLR_EL1_BT0		(BIT(35))
> -#define SCTLR_EL1_UCI		(BIT(26))
> -#define SCTLR_EL1_E0E		(BIT(24))
> -#define SCTLR_EL1_SPAN		(BIT(23))
> -#define SCTLR_EL1_NTWE		(BIT(18))
> -#define SCTLR_EL1_NTWI		(BIT(16))
> -#define SCTLR_EL1_UCT		(BIT(15))
> -#define SCTLR_EL1_DZE		(BIT(14))
> -#define SCTLR_EL1_UMA		(BIT(9))
> -#define SCTLR_EL1_SED		(BIT(8))
> -#define SCTLR_EL1_ITD		(BIT(7))
> -#define SCTLR_EL1_CP15BEN	(BIT(5))
> -#define SCTLR_EL1_SA0		(BIT(4))
> -
> -#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
> -			 (BIT(29)))
> -
>  #ifdef CONFIG_CPU_BIG_ENDIAN
>  #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
>  #else
> @@ -692,14 +532,17 @@
>  #endif
>  
>  #define INIT_SCTLR_EL1_MMU_OFF \
> -	(ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
> +	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
> +	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
>  
>  #define INIT_SCTLR_EL1_MMU_ON \
> -	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   | SCTLR_EL1_SA0   | \
> -	 SCTLR_EL1_SED  | SCTLR_ELx_I    | SCTLR_EL1_DZE  | SCTLR_EL1_UCT   | \
> -	 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
> -	 SCTLR_ELx_ATA  | SCTLR_EL1_ATA0 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI   | \
> -	 SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
> +	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
> +	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
> +	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
> +	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
> +	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
> +	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
> +	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
>  
>  /* MAIR_ELx memory attributes (used by Linux) */
>  #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
> @@ -712,387 +555,68 @@
>  /* Position the attr at the correct index */
>  #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
>  
> -/* id_aa64isar0 */
> -#define ID_AA64ISAR0_RNDR_SHIFT		60
> -#define ID_AA64ISAR0_TLB_SHIFT		56
> -#define ID_AA64ISAR0_TS_SHIFT		52
> -#define ID_AA64ISAR0_FHM_SHIFT		48
> -#define ID_AA64ISAR0_DP_SHIFT		44
> -#define ID_AA64ISAR0_SM4_SHIFT		40
> -#define ID_AA64ISAR0_SM3_SHIFT		36
> -#define ID_AA64ISAR0_SHA3_SHIFT		32
> -#define ID_AA64ISAR0_RDM_SHIFT		28
> -#define ID_AA64ISAR0_ATOMICS_SHIFT	20
> -#define ID_AA64ISAR0_CRC32_SHIFT	16
> -#define ID_AA64ISAR0_SHA2_SHIFT		12
> -#define ID_AA64ISAR0_SHA1_SHIFT		8
> -#define ID_AA64ISAR0_AES_SHIFT		4
> -
> -#define ID_AA64ISAR0_TLB_RANGE_NI	0x0
> -#define ID_AA64ISAR0_TLB_RANGE		0x2
> -
> -/* id_aa64isar1 */
> -#define ID_AA64ISAR1_I8MM_SHIFT		52
> -#define ID_AA64ISAR1_DGH_SHIFT		48
> -#define ID_AA64ISAR1_BF16_SHIFT		44
> -#define ID_AA64ISAR1_SPECRES_SHIFT	40
> -#define ID_AA64ISAR1_SB_SHIFT		36
> -#define ID_AA64ISAR1_FRINTTS_SHIFT	32
> -#define ID_AA64ISAR1_GPI_SHIFT		28
> -#define ID_AA64ISAR1_GPA_SHIFT		24
> -#define ID_AA64ISAR1_LRCPC_SHIFT	20
> -#define ID_AA64ISAR1_FCMA_SHIFT		16
> -#define ID_AA64ISAR1_JSCVT_SHIFT	12
> -#define ID_AA64ISAR1_API_SHIFT		8
> -#define ID_AA64ISAR1_APA_SHIFT		4
> -#define ID_AA64ISAR1_DPB_SHIFT		0
> -
> -#define ID_AA64ISAR1_APA_NI			0x0
> -#define ID_AA64ISAR1_APA_ARCHITECTED		0x1
> -#define ID_AA64ISAR1_APA_ARCH_EPAC		0x2
> -#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3
> -#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4
> -#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5
> -#define ID_AA64ISAR1_API_NI			0x0
> -#define ID_AA64ISAR1_API_IMP_DEF		0x1
> -#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2
> -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3
> -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4
> -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5
> -#define ID_AA64ISAR1_GPA_NI			0x0
> -#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1
> -#define ID_AA64ISAR1_GPI_NI			0x0
> -#define ID_AA64ISAR1_GPI_IMP_DEF		0x1
> -
>  /* id_aa64pfr0 */
> -#define ID_AA64PFR0_CSV3_SHIFT		60
> -#define ID_AA64PFR0_CSV2_SHIFT		56
> -#define ID_AA64PFR0_DIT_SHIFT		48
> -#define ID_AA64PFR0_AMU_SHIFT		44
> -#define ID_AA64PFR0_MPAM_SHIFT		40
> -#define ID_AA64PFR0_SEL2_SHIFT		36
> -#define ID_AA64PFR0_SVE_SHIFT		32
> -#define ID_AA64PFR0_RAS_SHIFT		28
> -#define ID_AA64PFR0_GIC_SHIFT		24
> -#define ID_AA64PFR0_ASIMD_SHIFT		20
> -#define ID_AA64PFR0_FP_SHIFT		16
> -#define ID_AA64PFR0_EL3_SHIFT		12
> -#define ID_AA64PFR0_EL2_SHIFT		8
> -#define ID_AA64PFR0_EL1_SHIFT		4
> -#define ID_AA64PFR0_EL0_SHIFT		0
> -
> -#define ID_AA64PFR0_AMU			0x1
> -#define ID_AA64PFR0_SVE			0x1
> -#define ID_AA64PFR0_RAS_V1		0x1
> -#define ID_AA64PFR0_RAS_V1P1		0x2
> -#define ID_AA64PFR0_FP_NI		0xf
> -#define ID_AA64PFR0_FP_SUPPORTED	0x0
> -#define ID_AA64PFR0_ASIMD_NI		0xf
> -#define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
> -#define ID_AA64PFR0_ELx_64BIT_ONLY	0x1
> -#define ID_AA64PFR0_ELx_32BIT_64BIT	0x2
> -
> -/* id_aa64pfr1 */
> -#define ID_AA64PFR1_MPAMFRAC_SHIFT	16
> -#define ID_AA64PFR1_RASFRAC_SHIFT	12
> -#define ID_AA64PFR1_MTE_SHIFT		8
> -#define ID_AA64PFR1_SSBS_SHIFT		4
> -#define ID_AA64PFR1_BT_SHIFT		0
> -
> -#define ID_AA64PFR1_SSBS_PSTATE_NI	0
> -#define ID_AA64PFR1_SSBS_PSTATE_ONLY	1
> -#define ID_AA64PFR1_SSBS_PSTATE_INSNS	2
> -#define ID_AA64PFR1_BT_BTI		0x1
> -
> -#define ID_AA64PFR1_MTE_NI		0x0
> -#define ID_AA64PFR1_MTE_EL0		0x1
> -#define ID_AA64PFR1_MTE			0x2
> -
> -/* id_aa64zfr0 */
> -#define ID_AA64ZFR0_F64MM_SHIFT		56
> -#define ID_AA64ZFR0_F32MM_SHIFT		52
> -#define ID_AA64ZFR0_I8MM_SHIFT		44
> -#define ID_AA64ZFR0_SM4_SHIFT		40
> -#define ID_AA64ZFR0_SHA3_SHIFT		32
> -#define ID_AA64ZFR0_BF16_SHIFT		20
> -#define ID_AA64ZFR0_BITPERM_SHIFT	16
> -#define ID_AA64ZFR0_AES_SHIFT		4
> -#define ID_AA64ZFR0_SVEVER_SHIFT	0
> -
> -#define ID_AA64ZFR0_F64MM		0x1
> -#define ID_AA64ZFR0_F32MM		0x1
> -#define ID_AA64ZFR0_I8MM		0x1
> -#define ID_AA64ZFR0_BF16		0x1
> -#define ID_AA64ZFR0_SM4			0x1
> -#define ID_AA64ZFR0_SHA3		0x1
> -#define ID_AA64ZFR0_BITPERM		0x1
> -#define ID_AA64ZFR0_AES			0x1
> -#define ID_AA64ZFR0_AES_PMULL		0x2
> -#define ID_AA64ZFR0_SVEVER_SVE2		0x1
> +#define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
> +#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
>  
>  /* id_aa64mmfr0 */
> -#define ID_AA64MMFR0_ECV_SHIFT		60
> -#define ID_AA64MMFR0_FGT_SHIFT		56
> -#define ID_AA64MMFR0_EXS_SHIFT		44
> -#define ID_AA64MMFR0_TGRAN4_2_SHIFT	40
> -#define ID_AA64MMFR0_TGRAN64_2_SHIFT	36
> -#define ID_AA64MMFR0_TGRAN16_2_SHIFT	32
> -#define ID_AA64MMFR0_TGRAN4_SHIFT	28
> -#define ID_AA64MMFR0_TGRAN64_SHIFT	24
> -#define ID_AA64MMFR0_TGRAN16_SHIFT	20
> -#define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
> -#define ID_AA64MMFR0_SNSMEM_SHIFT	12
> -#define ID_AA64MMFR0_BIGENDEL_SHIFT	8
> -#define ID_AA64MMFR0_ASID_SHIFT		4
> -#define ID_AA64MMFR0_PARANGE_SHIFT	0
> -
> -#define ID_AA64MMFR0_ASID_8		0x0
> -#define ID_AA64MMFR0_ASID_16		0x2
> -
> -#define ID_AA64MMFR0_TGRAN4_NI			0xf
> -#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0
> -#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7
> -#define ID_AA64MMFR0_TGRAN64_NI			0xf
> -#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0
> -#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7
> -#define ID_AA64MMFR0_TGRAN16_NI			0x0
> -#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1
> -#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf
> -
> -#define ID_AA64MMFR0_PARANGE_32		0x0
> -#define ID_AA64MMFR0_PARANGE_36		0x1
> -#define ID_AA64MMFR0_PARANGE_40		0x2
> -#define ID_AA64MMFR0_PARANGE_42		0x3
> -#define ID_AA64MMFR0_PARANGE_44		0x4
> -#define ID_AA64MMFR0_PARANGE_48		0x5
> -#define ID_AA64MMFR0_PARANGE_52		0x6
> +#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
> +#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
> +#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
> +#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
> +#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
> +#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
>  
>  #define ARM64_MIN_PARANGE_BITS		32
>  
> -#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0
> -#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1
> -#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2
> -#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
>  
>  #ifdef CONFIG_ARM64_PA_BITS_52
> -#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52
> +#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
>  #else
> -#define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
> +#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
>  #endif
>  
> -/* id_aa64mmfr1 */
> -#define ID_AA64MMFR1_ETS_SHIFT		36
> -#define ID_AA64MMFR1_TWED_SHIFT		32
> -#define ID_AA64MMFR1_XNX_SHIFT		28
> -#define ID_AA64MMFR1_SPECSEI_SHIFT	24
> -#define ID_AA64MMFR1_PAN_SHIFT		20
> -#define ID_AA64MMFR1_LOR_SHIFT		16
> -#define ID_AA64MMFR1_HPD_SHIFT		12
> -#define ID_AA64MMFR1_VHE_SHIFT		8
> -#define ID_AA64MMFR1_VMIDBITS_SHIFT	4
> -#define ID_AA64MMFR1_HADBS_SHIFT	0
> -
> -#define ID_AA64MMFR1_VMIDBITS_8		0
> -#define ID_AA64MMFR1_VMIDBITS_16	2
> -
> -/* id_aa64mmfr2 */
> -#define ID_AA64MMFR2_E0PD_SHIFT		60
> -#define ID_AA64MMFR2_EVT_SHIFT		56
> -#define ID_AA64MMFR2_BBM_SHIFT		52
> -#define ID_AA64MMFR2_TTL_SHIFT		48
> -#define ID_AA64MMFR2_FWB_SHIFT		40
> -#define ID_AA64MMFR2_IDS_SHIFT		36
> -#define ID_AA64MMFR2_AT_SHIFT		32
> -#define ID_AA64MMFR2_ST_SHIFT		28
> -#define ID_AA64MMFR2_NV_SHIFT		24
> -#define ID_AA64MMFR2_CCIDX_SHIFT	20
> -#define ID_AA64MMFR2_LVA_SHIFT		16
> -#define ID_AA64MMFR2_IESB_SHIFT		12
> -#define ID_AA64MMFR2_LSM_SHIFT		8
> -#define ID_AA64MMFR2_UAO_SHIFT		4
> -#define ID_AA64MMFR2_CNP_SHIFT		0
> -
> -/* id_aa64dfr0 */
> -#define ID_AA64DFR0_MTPMU_SHIFT		48
> -#define ID_AA64DFR0_TRBE_SHIFT		44
> -#define ID_AA64DFR0_TRACE_FILT_SHIFT	40
> -#define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
> -#define ID_AA64DFR0_PMSVER_SHIFT	32
> -#define ID_AA64DFR0_CTX_CMPS_SHIFT	28
> -#define ID_AA64DFR0_WRPS_SHIFT		20
> -#define ID_AA64DFR0_BRPS_SHIFT		12
> -#define ID_AA64DFR0_PMUVER_SHIFT	8
> -#define ID_AA64DFR0_TRACEVER_SHIFT	4
> -#define ID_AA64DFR0_DEBUGVER_SHIFT	0
> -
> -#define ID_AA64DFR0_PMUVER_8_0		0x1
> -#define ID_AA64DFR0_PMUVER_8_1		0x4
> -#define ID_AA64DFR0_PMUVER_8_4		0x5
> -#define ID_AA64DFR0_PMUVER_8_5		0x6
> -#define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
> -
> -#define ID_AA64DFR0_PMSVER_8_2		0x1
> -#define ID_AA64DFR0_PMSVER_8_3		0x2
> -
> -#define ID_DFR0_PERFMON_SHIFT		24
> -
> -#define ID_DFR0_PERFMON_8_0		0x3
> -#define ID_DFR0_PERFMON_8_1		0x4
> -#define ID_DFR0_PERFMON_8_4		0x5
> -#define ID_DFR0_PERFMON_8_5		0x6
> -
> -#define ID_ISAR4_SWP_FRAC_SHIFT		28
> -#define ID_ISAR4_PSR_M_SHIFT		24
> -#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT	20
> -#define ID_ISAR4_BARRIER_SHIFT		16
> -#define ID_ISAR4_SMC_SHIFT		12
> -#define ID_ISAR4_WRITEBACK_SHIFT	8
> -#define ID_ISAR4_WITHSHIFTS_SHIFT	4
> -#define ID_ISAR4_UNPRIV_SHIFT		0
> -
> -#define ID_DFR1_MTPMU_SHIFT		0
> -
> -#define ID_ISAR0_DIVIDE_SHIFT		24
> -#define ID_ISAR0_DEBUG_SHIFT		20
> -#define ID_ISAR0_COPROC_SHIFT		16
> -#define ID_ISAR0_CMPBRANCH_SHIFT	12
> -#define ID_ISAR0_BITFIELD_SHIFT		8
> -#define ID_ISAR0_BITCOUNT_SHIFT		4
> -#define ID_ISAR0_SWAP_SHIFT		0
> -
> -#define ID_ISAR5_RDM_SHIFT		24
> -#define ID_ISAR5_CRC32_SHIFT		16
> -#define ID_ISAR5_SHA2_SHIFT		12
> -#define ID_ISAR5_SHA1_SHIFT		8
> -#define ID_ISAR5_AES_SHIFT		4
> -#define ID_ISAR5_SEVL_SHIFT		0
> -
> -#define ID_ISAR6_I8MM_SHIFT		24
> -#define ID_ISAR6_BF16_SHIFT		20
> -#define ID_ISAR6_SPECRES_SHIFT		16
> -#define ID_ISAR6_SB_SHIFT		12
> -#define ID_ISAR6_FHM_SHIFT		8
> -#define ID_ISAR6_DP_SHIFT		4
> -#define ID_ISAR6_JSCVT_SHIFT		0
> -
> -#define ID_MMFR0_INNERSHR_SHIFT		28
> -#define ID_MMFR0_FCSE_SHIFT		24
> -#define ID_MMFR0_AUXREG_SHIFT		20
> -#define ID_MMFR0_TCM_SHIFT		16
> -#define ID_MMFR0_SHARELVL_SHIFT		12
> -#define ID_MMFR0_OUTERSHR_SHIFT		8
> -#define ID_MMFR0_PMSA_SHIFT		4
> -#define ID_MMFR0_VMSA_SHIFT		0
> -
> -#define ID_MMFR4_EVT_SHIFT		28
> -#define ID_MMFR4_CCIDX_SHIFT		24
> -#define ID_MMFR4_LSM_SHIFT		20
> -#define ID_MMFR4_HPDS_SHIFT		16
> -#define ID_MMFR4_CNP_SHIFT		12
> -#define ID_MMFR4_XNX_SHIFT		8
> -#define ID_MMFR4_AC2_SHIFT		4
> -#define ID_MMFR4_SPECSEI_SHIFT		0
> -
> -#define ID_MMFR5_ETS_SHIFT		0
> -
> -#define ID_PFR0_DIT_SHIFT		24
> -#define ID_PFR0_CSV2_SHIFT		16
> -#define ID_PFR0_STATE3_SHIFT		12
> -#define ID_PFR0_STATE2_SHIFT		8
> -#define ID_PFR0_STATE1_SHIFT		4
> -#define ID_PFR0_STATE0_SHIFT		0
> -
> -#define ID_DFR0_PERFMON_SHIFT		24
> -#define ID_DFR0_MPROFDBG_SHIFT		20
> -#define ID_DFR0_MMAPTRC_SHIFT		16
> -#define ID_DFR0_COPTRC_SHIFT		12
> -#define ID_DFR0_MMAPDBG_SHIFT		8
> -#define ID_DFR0_COPSDBG_SHIFT		4
> -#define ID_DFR0_COPDBG_SHIFT		0
> -
> -#define ID_PFR2_SSBS_SHIFT		4
> -#define ID_PFR2_CSV3_SHIFT		0
> -
> -#define MVFR0_FPROUND_SHIFT		28
> -#define MVFR0_FPSHVEC_SHIFT		24
> -#define MVFR0_FPSQRT_SHIFT		20
> -#define MVFR0_FPDIVIDE_SHIFT		16
> -#define MVFR0_FPTRAP_SHIFT		12
> -#define MVFR0_FPDP_SHIFT		8
> -#define MVFR0_FPSP_SHIFT		4
> -#define MVFR0_SIMD_SHIFT		0
> -
> -#define MVFR1_SIMDFMAC_SHIFT		28
> -#define MVFR1_FPHP_SHIFT		24
> -#define MVFR1_SIMDHP_SHIFT		20
> -#define MVFR1_SIMDSP_SHIFT		16
> -#define MVFR1_SIMDINT_SHIFT		12
> -#define MVFR1_SIMDLS_SHIFT		8
> -#define MVFR1_FPDNAN_SHIFT		4
> -#define MVFR1_FPFTZ_SHIFT		0
> -
> -#define ID_PFR1_GIC_SHIFT		28
> -#define ID_PFR1_VIRT_FRAC_SHIFT		24
> -#define ID_PFR1_SEC_FRAC_SHIFT		20
> -#define ID_PFR1_GENTIMER_SHIFT		16
> -#define ID_PFR1_VIRTUALIZATION_SHIFT	12
> -#define ID_PFR1_MPROGMOD_SHIFT		8
> -#define ID_PFR1_SECURITY_SHIFT		4
> -#define ID_PFR1_PROGMOD_SHIFT		0
> -
>  #if defined(CONFIG_ARM64_4K_PAGES)
> -#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT
> -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
> -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
> -#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN4_2_SHIFT
> +#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
> +#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
> +#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
>  #elif defined(CONFIG_ARM64_16K_PAGES)
> -#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT
> -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
> -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
> -#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN16_2_SHIFT
> +#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
> +#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
> +#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
>  #elif defined(CONFIG_ARM64_64K_PAGES)
> -#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT
> -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
> -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
> -#define ID_AA64MMFR0_TGRAN_2_SHIFT		ID_AA64MMFR0_TGRAN64_2_SHIFT
> +#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
> +#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
> +#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
> +#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
>  #endif
>  
> -#define MVFR2_FPMISC_SHIFT		4
> -#define MVFR2_SIMDMISC_SHIFT		0
> -
> -#define DCZID_DZP_SHIFT			4
> -#define DCZID_BS_SHIFT			0
> +#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
> +#define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
>  
> -/*
> - * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
> - * are reserved by the SVE architecture for future expansion of the LEN
> - * field, with compatible semantics.
> - */
> -#define ZCR_ELx_LEN_SHIFT	0
> -#define ZCR_ELx_LEN_SIZE	9
> -#define ZCR_ELx_LEN_MASK	0x1ff
> +#define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
> +#define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
>  
>  #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
>  #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
> -#define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
> -
> -/* TCR EL1 Bit Definitions */
> -#define SYS_TCR_EL1_TCMA1	(BIT(58))
> -#define SYS_TCR_EL1_TCMA0	(BIT(57))
>  
>  /* GCR_EL1 Definitions */
>  #define SYS_GCR_EL1_RRND	(BIT(16))
>  #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
>  
> +#define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
> +
>  /* RGSR_EL1 Definitions */
>  #define SYS_RGSR_EL1_TAG_MASK	0xfUL
>  #define SYS_RGSR_EL1_SEED_SHIFT	8
>  #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
>  
> -/* GMID_EL1 field definitions */
> -#define SYS_GMID_EL1_BS_SHIFT	0
> -#define SYS_GMID_EL1_BS_SIZE	4
> -
>  /* TFSR{,E0}_EL1 bit definitions */
>  #define SYS_TFSR_EL1_TF0_SHIFT	0
>  #define SYS_TFSR_EL1_TF1_SHIFT	1
> @@ -1103,6 +627,7 @@
>  #define SYS_MPIDR_SAFE_VAL	(BIT(31))
>  
>  #define TRFCR_ELx_TS_SHIFT		5
> +#define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
>  #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
>  #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
>  #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
> @@ -1110,7 +635,6 @@
>  #define TRFCR_ELx_ExTRE			BIT(1)
>  #define TRFCR_ELx_E0TRE			BIT(0)
>  
> -
>  /* GIC Hypervisor interface registers */
>  /* ICH_MISR_EL2 bit definitions */
>  #define ICH_MISR_EOI		(1 << 0)
> @@ -1137,6 +661,7 @@
>  #define ICH_HCR_TC		(1 << 10)
>  #define ICH_HCR_TALL0		(1 << 11)
>  #define ICH_HCR_TALL1		(1 << 12)
> +#define ICH_HCR_TDIR		(1 << 14)
>  #define ICH_HCR_EOIcount_SHIFT	27
>  #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
>  
> @@ -1169,49 +694,60 @@
>  #define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
>  #define ICH_VTR_A3V_SHIFT	21
>  #define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
> +#define ICH_VTR_TDS_SHIFT	19
> +#define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
> +
> +/*
> + * Permission Indirection Extension (PIE) permission encodings.
> + * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
> + */
> +#define PIE_NONE_O	0x0
> +#define PIE_R_O		0x1
> +#define PIE_X_O		0x2
> +#define PIE_RX_O	0x3
> +#define PIE_RW_O	0x5
> +#define PIE_RWnX_O	0x6
> +#define PIE_RWX_O	0x7
> +#define PIE_R		0x8
> +#define PIE_GCS		0x9
> +#define PIE_RX		0xa
> +#define PIE_RW		0xc
> +#define PIE_RWX		0xe
> +
> +#define PIRx_ELx_PERM(idx, perm)	((perm) << ((idx) * 4))
>  
>  #define ARM64_FEATURE_FIELD_BITS	4
>  
> -/* Create a mask for the feature bits of the specified feature. */
> -#define ARM64_FEATURE_MASK(x)	(GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
> +/* Defined for compatibility only, do not add new users. */
> +#define ARM64_FEATURE_MASK(x)	(x##_MASK)
>  
>  #ifdef __ASSEMBLY__
>  
> -	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> -	.equ	.L__reg_num_x\num, \num
> -	.endr
> -	.equ	.L__reg_num_xzr, 31
> -
>  	.macro	mrs_s, rt, sreg
> -	 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
> +	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
>  	.endm
>  
>  	.macro	msr_s, sreg, rt
> -	__emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
> +	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
>  	.endm
>  
>  #else
>  
> +#include <linux/bitfield.h>
>  #include <linux/build_bug.h>
>  #include <linux/types.h>
>  #include <asm/alternative.h>
>  
> -#define __DEFINE_MRS_MSR_S_REGNUM				\
> -"	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
> -"	.equ	.L__reg_num_x\\num, \\num\n"			\
> -"	.endr\n"						\
> -"	.equ	.L__reg_num_xzr, 31\n"
> -
>  #define DEFINE_MRS_S						\
> -	__DEFINE_MRS_MSR_S_REGNUM				\
> +	__DEFINE_ASM_GPR_NUMS					\
>  "	.macro	mrs_s, rt, sreg\n"				\
> -	__emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))	\
> +	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
>  "	.endm\n"
>  
>  #define DEFINE_MSR_S						\
> -	__DEFINE_MRS_MSR_S_REGNUM				\
> +	__DEFINE_ASM_GPR_NUMS					\
>  "	.macro	msr_s, sreg, rt\n"				\
> -	__emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))	\
> +	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
>  "	.endm\n"
>  
>  #define UNDEFINE_MRS_S						\
> @@ -1291,6 +827,15 @@
>  	par;								\
>  })
>  
> +#define SYS_FIELD_GET(reg, field, val)		\
> +		 FIELD_GET(reg##_##field##_MASK, val)
> +
> +#define SYS_FIELD_PREP(reg, field, val)		\
> +		 FIELD_PREP(reg##_##field##_MASK, val)
> +
> +#define SYS_FIELD_PREP_ENUM(reg, field, val)		\
> +		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
> +
>  #endif
>  
>  #endif	/* __ASM_SYSREG_H */
> diff --git a/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c b/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
> index b90580840b22..8e5bd07a3727 100644
> --- a/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
> +++ b/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c
> @@ -146,8 +146,8 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu)
>  
>  	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
>  
> -	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL0), val);
> -	return el0 == ID_AA64PFR0_ELx_64BIT_ONLY;
> +	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
> +	return el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY;
>  }
>  
>  int main(void)
> diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
> index f5b6cb3a0019..866002917441 100644
> --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
> +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c
> @@ -116,12 +116,12 @@ static void reset_debug_state(void)
>  
>  	/* Reset all bcr/bvr/wcr/wvr registers */
>  	dfr0 = read_sysreg(id_aa64dfr0_el1);
> -	brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), dfr0);
> +	brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), dfr0);
>  	for (i = 0; i <= brps; i++) {
>  		write_dbgbcr(i, 0);
>  		write_dbgbvr(i, 0);
>  	}
> -	wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), dfr0);
> +	wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), dfr0);
>  	for (i = 0; i <= wrps; i++) {
>  		write_dbgwcr(i, 0);
>  		write_dbgwvr(i, 0);
> @@ -418,7 +418,7 @@ static void guest_code_ss(int test_cnt)
>  
>  static int debug_version(uint64_t id_aa64dfr0)
>  {
> -	return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), id_aa64dfr0);
> +	return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), id_aa64dfr0);
>  }
>  
>  static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)
> @@ -539,14 +539,14 @@ void test_guest_debug_exceptions_all(uint64_t aa64dfr0)
>  	int b, w, c;
>  
>  	/* Number of breakpoints */
> -	brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), aa64dfr0) + 1;
> +	brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), aa64dfr0) + 1;
>  	__TEST_REQUIRE(brp_num >= 2, "At least two breakpoints are required");
>  
>  	/* Number of watchpoints */
> -	wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), aa64dfr0) + 1;
> +	wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), aa64dfr0) + 1;
>  
>  	/* Number of context aware breakpoints */
> -	ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_CTX_CMPS), aa64dfr0) + 1;
> +	ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), aa64dfr0) + 1;
>  
>  	pr_debug("%s brp_num:%d, wrp_num:%d, ctx_brp_num:%d\n", __func__,
>  		 brp_num, wrp_num, ctx_brp_num);
> diff --git a/tools/testing/selftests/kvm/aarch64/page_fault_test.c b/tools/testing/selftests/kvm/aarch64/page_fault_test.c
> index 47bb914ab2fa..975d28be3cca 100644
> --- a/tools/testing/selftests/kvm/aarch64/page_fault_test.c
> +++ b/tools/testing/selftests/kvm/aarch64/page_fault_test.c
> @@ -96,14 +96,14 @@ static bool guest_check_lse(void)
>  	uint64_t isar0 = read_sysreg(id_aa64isar0_el1);
>  	uint64_t atomic;
>  
> -	atomic = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS), isar0);
> +	atomic = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC), isar0);
>  	return atomic >= 2;
>  }
>  
>  static bool guest_check_dc_zva(void)
>  {
>  	uint64_t dczid = read_sysreg(dczid_el0);
> -	uint64_t dzp = FIELD_GET(ARM64_FEATURE_MASK(DCZID_DZP), dczid);
> +	uint64_t dzp = FIELD_GET(ARM64_FEATURE_MASK(DCZID_EL0_DZP), dczid);
>  
>  	return dzp == 0;
>  }
> @@ -196,7 +196,7 @@ static bool guest_set_ha(void)
>  	uint64_t hadbs, tcr;
>  
>  	/* Skip if HA is not supported. */
> -	hadbs = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_HADBS), mmfr1);
> +	hadbs = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS), mmfr1);
>  	if (hadbs == 0)
>  		return false;
>  
> diff --git a/tools/testing/selftests/kvm/lib/aarch64/processor.c b/tools/testing/selftests/kvm/lib/aarch64/processor.c
> index 3a0259e25335..6fe12e985ba5 100644
> --- a/tools/testing/selftests/kvm/lib/aarch64/processor.c
> +++ b/tools/testing/selftests/kvm/lib/aarch64/processor.c
> @@ -518,9 +518,9 @@ void aarch64_get_supported_page_sizes(uint32_t ipa,
>  	err = ioctl(vcpu_fd, KVM_GET_ONE_REG, &reg);
>  	TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));
>  
> -	*ps4k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4), val) != 0xf;
> -	*ps64k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64), val) == 0;
> -	*ps16k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN16), val) != 0;
> +	*ps4k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN4), val) != 0xf;
> +	*ps64k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN64), val) == 0;
> +	*ps16k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN16), val) != 0;
>  
>  	close(vcpu_fd);
>  	close(vm_fd);


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Re: [PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Mark Brown]

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On Wed, Oct 18, 2023 at 01:57:31PM +0200, Eric Auger wrote:
> On 10/11/23 21:57, Oliver Upton wrote:

> >  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
> >  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
> >  #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
> > +#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))

> could you comment on the *DIT* addictions, what is it for?

DIT is data independent timing, this tells the processor to ensure that
instructions take a constant time regardless of the data they are
handling.

Note that this file is just a copy of arch/arm64/include/asm/gpr-num.h,
the main purpose here is to sync with the original.

> > +/*
> > + * Automatically generated definitions for system registers, the
> > + * manual encodings below are in the process of being converted to
> > + * come from here. The header relies on the definition of sys_reg()
> > + * earlier in this file.
> > + */
> > +#include "asm/sysreg-defs.h"

> strange to have this include in the middle of the file

It relies on defines from earlier in the header.

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Re: [PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Eric Auger]

Hi Mark, Oliver,

On 10/18/23 14:16, Mark Brown wrote:
> On Wed, Oct 18, 2023 at 01:57:31PM +0200, Eric Auger wrote:
>> On 10/11/23 21:57, Oliver Upton wrote:
> 
>>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>>>  #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
>>> +#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
> 
>> could you comment on the *DIT* addictions, what is it for?
> 
> DIT is data independent timing, this tells the processor to ensure that
> instructions take a constant time regardless of the data they are
> handling.

> 
> Note that this file is just a copy of arch/arm64/include/asm/gpr-num.h,
> the main purpose here is to sync with the original.

Ah thanks. that's helpful for me to understand where this gpr-num.h
comes from. This could be documented in the commit msg though.

Something like:

adding tools/arch/arm64/include/asm/gpr-num.h matching linux
arch/arm64/include/asm/gpr-num.h

and syncing tools/arch/arm64/include/asm/sysreg.h with the fellow header
in the linux tree.

tbh I did not initially understand that all this diffstat was aimed to
match the linux arch/arm64/include/asm/sysreg.h. Now diffing both I have
some diffs. Doesn't it need a refresh?

Thanks

Eric
> 
>>> +/*
>>> + * Automatically generated definitions for system registers, the
>>> + * manual encodings below are in the process of being converted to
>>> + * come from here. The header relies on the definition of sys_reg()
>>> + * earlier in this file.
>>> + */
>>> +#include "asm/sysreg-defs.h"
> 
>> strange to have this include in the middle of the file
> 
> It relies on defines from earlier in the header.


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Re: [PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Oliver Upton]

Hi Eric,

Thanks for reviewing the series.

On Wed, Oct 18, 2023 at 03:06:12PM +0200, Eric Auger wrote:
> Hi Mark, Oliver,
> 
> On 10/18/23 14:16, Mark Brown wrote:
> > On Wed, Oct 18, 2023 at 01:57:31PM +0200, Eric Auger wrote:
> >> On 10/11/23 21:57, Oliver Upton wrote:
> > 
> >>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
> >>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
> >>>  #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
> >>> +#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
> > 
> >> could you comment on the *DIT* addictions, what is it for?
> > 
> > DIT is data independent timing, this tells the processor to ensure that
> > instructions take a constant time regardless of the data they are
> > handling.
> 
> > 
> > Note that this file is just a copy of arch/arm64/include/asm/gpr-num.h,
> > the main purpose here is to sync with the original.
> 
> Ah thanks. that's helpful for me to understand where this gpr-num.h
> comes from. This could be documented in the commit msg though.
> 
> Something like:
> 
> adding tools/arch/arm64/include/asm/gpr-num.h matching linux
> arch/arm64/include/asm/gpr-num.h
> 
> and syncing tools/arch/arm64/include/asm/sysreg.h with the fellow header
> in the linux tree.

Yeah, I could've spelled it out a bit more. I already cracked this off
of an even larger patch from before I picked up the series because the
diff was massive.

> tbh I did not initially understand that all this diffstat was aimed to
> match the linux arch/arm64/include/asm/sysreg.h. Now diffing both I have
> some diffs. Doesn't it need a refresh?

I'm worried it is a fool's errand at this point to keep the two in sync,
as I'm sure there will be more in -rc1. The tools copy of sysreg.h isn't
a verbatim copy either, there are some deliberate deletions in there as
well.

I've taken this as is, we can always come back and update the headers
afterwards if we find a need for it

-- 
Thanks,
Oliver

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Re: [PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Eric Auger]

Hi Oliver,

On 10/19/23 02:06, Oliver Upton wrote:
> Hi Eric,
> 
> Thanks for reviewing the series.
> 
> On Wed, Oct 18, 2023 at 03:06:12PM +0200, Eric Auger wrote:
>> Hi Mark, Oliver,
>>
>> On 10/18/23 14:16, Mark Brown wrote:
>>> On Wed, Oct 18, 2023 at 01:57:31PM +0200, Eric Auger wrote:
>>>> On 10/11/23 21:57, Oliver Upton wrote:
>>>
>>>>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>>>>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>>>>>  #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
>>>>> +#define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
>>>
>>>> could you comment on the *DIT* addictions, what is it for?
>>>
>>> DIT is data independent timing, this tells the processor to ensure that
>>> instructions take a constant time regardless of the data they are
>>> handling.
>>
>>>
>>> Note that this file is just a copy of arch/arm64/include/asm/gpr-num.h,
>>> the main purpose here is to sync with the original.
>>
>> Ah thanks. that's helpful for me to understand where this gpr-num.h
>> comes from. This could be documented in the commit msg though.
>>
>> Something like:
>>
>> adding tools/arch/arm64/include/asm/gpr-num.h matching linux
>> arch/arm64/include/asm/gpr-num.h
>>
>> and syncing tools/arch/arm64/include/asm/sysreg.h with the fellow header
>> in the linux tree.
> 
> Yeah, I could've spelled it out a bit more. I already cracked this off
> of an even larger patch from before I picked up the series because the
> diff was massive.
> 
>> tbh I did not initially understand that all this diffstat was aimed to
>> match the linux arch/arm64/include/asm/sysreg.h. Now diffing both I have
>> some diffs. Doesn't it need a refresh?
> 
> I'm worried it is a fool's errand at this point to keep the two in sync,
> as I'm sure there will be more in -rc1. The tools copy of sysreg.h isn't
> a verbatim copy either, there are some deliberate deletions in there as
> well.
> 
> I've taken this as is, we can always come back and update the headers
> afterwards if we find a need for it

OK np. I did not notice you picked the series up and I jumped in too
late. Anyway that was worthwhile for my education ;-)

Eric
> 


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Re: [PATCH v3 4/5] tools headers arm64: Update sysreg.h with kernel sources

[Oliver Upton]

On Thu, Oct 19, 2023 at 10:43:34AM +0200, Eric Auger wrote:

[...]

> OK np. I did not notice you picked the series up and I jumped in too
> late. Anyway that was worthwhile for my education ;-)

And as always, patches welcome :) We're getting close to the next
release and I'd like to have the majority of the kvmarm PR baking in
next for a while. But fixes are easy to stack on top.

Thanks again for the reviews.

-- 
Best,
Oliver

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[PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Oliver Upton]

From: Jing Zhang <jingzhangos@google.com>

Add tests to verify setting ID registers from userspace is handled
correctly by KVM. Also add a test case to use ioctl
KVM_ARM_GET_REG_WRITABLE_MASKS to get writable masks.

Signed-off-by: Jing Zhang <jingzhangos@google.com>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
 tools/testing/selftests/kvm/Makefile          |   1 +
 .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++++++++++
 2 files changed, 480 insertions(+)
 create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 07b3f4dc1a77..4f4f6ad025f4 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -156,6 +156,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/debug-exceptions
 TEST_GEN_PROGS_aarch64 += aarch64/hypercalls
 TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test
 TEST_GEN_PROGS_aarch64 += aarch64/psci_test
+TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs
 TEST_GEN_PROGS_aarch64 += aarch64/smccc_filter
 TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config
 TEST_GEN_PROGS_aarch64 += aarch64/vgic_init
diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
new file mode 100644
index 000000000000..5c0718fd1705
--- /dev/null
+++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
@@ -0,0 +1,479 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * set_id_regs - Test for setting ID register from usersapce.
+ *
+ * Copyright (c) 2023 Google LLC.
+ *
+ *
+ * Test that KVM supports setting ID registers from userspace and handles the
+ * feature set correctly.
+ */
+
+#include <stdint.h>
+#include "kvm_util.h"
+#include "processor.h"
+#include "test_util.h"
+#include <linux/bitfield.h>
+
+enum ftr_type {
+	FTR_EXACT,			/* Use a predefined safe value */
+	FTR_LOWER_SAFE,			/* Smaller value is safe */
+	FTR_HIGHER_SAFE,		/* Bigger value is safe */
+	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */
+	FTR_END,			/* Mark the last ftr bits */
+};
+
+#define FTR_SIGNED	true	/* Value should be treated as signed */
+#define FTR_UNSIGNED	false	/* Value should be treated as unsigned */
+
+struct reg_ftr_bits {
+	char *name;
+	bool sign;
+	enum ftr_type type;
+	uint8_t shift;
+	uint64_t mask;
+	int64_t safe_val;
+};
+
+struct test_feature_reg {
+	uint32_t reg;
+	const struct reg_ftr_bits *ftr_bits;
+};
+
+#define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL)	\
+	{								\
+		.name = #NAME,						\
+		.sign = SIGNED,						\
+		.type = TYPE,						\
+		.shift = SHIFT,						\
+		.mask = MASK,						\
+		.safe_val = SAFE_VAL,					\
+	}
+
+#define REG_FTR_BITS(type, reg, field, safe_val) \
+	__REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
+		       reg##_##field##_MASK, safe_val)
+
+#define S_REG_FTR_BITS(type, reg, field, safe_val) \
+	__REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
+		       reg##_##field##_MASK, safe_val)
+
+#define REG_FTR_END					\
+	{						\
+		.type = FTR_END,			\
+	}
+
+static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
+	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
+	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
+	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
+	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
+	REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
+	REG_FTR_END,
+};
+
+static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
+	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
+	REG_FTR_END,
+};
+
+#define TEST_REG(id, table)			\
+	{					\
+		.reg = id,			\
+		.ftr_bits = &((table)[0]),	\
+	}
+
+static struct test_feature_reg test_regs[] = {
+	TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
+	TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
+	TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
+	TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
+	TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
+	TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
+	TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
+	TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
+	TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
+	TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
+};
+
+#define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
+
+static void guest_code(void)
+{
+	GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
+	GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
+	GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
+
+	GUEST_DONE();
+}
+
+/* Return a safe value to a given ftr_bits an ftr value */
+uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
+{
+	uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
+
+	if (ftr_bits->type == FTR_UNSIGNED) {
+		switch (ftr_bits->type) {
+		case FTR_EXACT:
+			ftr = ftr_bits->safe_val;
+			break;
+		case FTR_LOWER_SAFE:
+			if (ftr > 0)
+				ftr--;
+			break;
+		case FTR_HIGHER_SAFE:
+			if (ftr < ftr_max)
+				ftr++;
+			break;
+		case FTR_HIGHER_OR_ZERO_SAFE:
+			if (ftr == ftr_max)
+				ftr = 0;
+			else if (ftr != 0)
+				ftr++;
+			break;
+		default:
+			break;
+		}
+	} else if (ftr != ftr_max) {
+		switch (ftr_bits->type) {
+		case FTR_EXACT:
+			ftr = ftr_bits->safe_val;
+			break;
+		case FTR_LOWER_SAFE:
+			if (ftr > 0)
+				ftr--;
+			break;
+		case FTR_HIGHER_SAFE:
+			if (ftr < ftr_max - 1)
+				ftr++;
+			break;
+		case FTR_HIGHER_OR_ZERO_SAFE:
+			if (ftr != 0 && ftr != ftr_max - 1)
+				ftr++;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return ftr;
+}
+
+/* Return an invalid value to a given ftr_bits an ftr value */
+uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
+{
+	uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
+
+	if (ftr_bits->type == FTR_UNSIGNED) {
+		switch (ftr_bits->type) {
+		case FTR_EXACT:
+			ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
+			break;
+		case FTR_LOWER_SAFE:
+			ftr++;
+			break;
+		case FTR_HIGHER_SAFE:
+			ftr--;
+			break;
+		case FTR_HIGHER_OR_ZERO_SAFE:
+			if (ftr == 0)
+				ftr = ftr_max;
+			else
+				ftr--;
+			break;
+		default:
+			break;
+		}
+	} else if (ftr != ftr_max) {
+		switch (ftr_bits->type) {
+		case FTR_EXACT:
+			ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
+			break;
+		case FTR_LOWER_SAFE:
+			ftr++;
+			break;
+		case FTR_HIGHER_SAFE:
+			ftr--;
+			break;
+		case FTR_HIGHER_OR_ZERO_SAFE:
+			if (ftr == 0)
+				ftr = ftr_max - 1;
+			else
+				ftr--;
+			break;
+		default:
+			break;
+		}
+	} else {
+		ftr = 0;
+	}
+
+	return ftr;
+}
+
+static void test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
+				 const struct reg_ftr_bits *ftr_bits)
+{
+	uint8_t shift = ftr_bits->shift;
+	uint64_t mask = ftr_bits->mask;
+	uint64_t val, new_val, ftr;
+
+	vcpu_get_reg(vcpu, reg, &val);
+	ftr = (val & mask) >> shift;
+
+	ftr = get_safe_value(ftr_bits, ftr);
+
+	ftr <<= shift;
+	val &= ~mask;
+	val |= ftr;
+
+	vcpu_set_reg(vcpu, reg, val);
+	vcpu_get_reg(vcpu, reg, &new_val);
+	TEST_ASSERT_EQ(new_val, val);
+}
+
+static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
+			      const struct reg_ftr_bits *ftr_bits)
+{
+	uint8_t shift = ftr_bits->shift;
+	uint64_t mask = ftr_bits->mask;
+	uint64_t val, old_val, ftr;
+	int r;
+
+	vcpu_get_reg(vcpu, reg, &val);
+	ftr = (val & mask) >> shift;
+
+	ftr = get_invalid_value(ftr_bits, ftr);
+
+	old_val = val;
+	ftr <<= shift;
+	val &= ~mask;
+	val |= ftr;
+
+	r = __vcpu_set_reg(vcpu, reg, val);
+	TEST_ASSERT(r < 0 && errno == EINVAL,
+		    "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
+
+	vcpu_get_reg(vcpu, reg, &val);
+	TEST_ASSERT_EQ(val, old_val);
+}
+
+static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only)
+{
+	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
+	struct reg_mask_range range = {
+		.addr = (__u64)masks,
+	};
+	int ret;
+
+	/* KVM should return error when reserved field is not zero */
+	range.reserved[0] = 1;
+	ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
+	TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
+
+	/* Get writable masks for feature ID registers */
+	memset(range.reserved, 0, sizeof(range.reserved));
+	vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
+
+	for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
+		const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
+		uint32_t reg_id = test_regs[i].reg;
+		uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
+		int idx;
+
+		/* Get the index to masks array for the idreg */
+		idx = KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(reg_id), sys_reg_Op1(reg_id),
+						   sys_reg_CRn(reg_id), sys_reg_CRm(reg_id),
+						   sys_reg_Op2(reg_id));
+
+		for (int j = 0;  ftr_bits[j].type != FTR_END; j++) {
+			/* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
+			if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
+				ksft_test_result_skip("%s on AARCH64 only system\n",
+						      ftr_bits[j].name);
+				continue;
+			}
+
+			/* Make sure the feature field is writable */
+			TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
+
+			test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
+			test_reg_set_success(vcpu, reg, &ftr_bits[j]);
+
+			ksft_test_result_pass("%s\n", ftr_bits[j].name);
+		}
+	}
+}
+
+static void test_guest_reg_read(struct kvm_vcpu *vcpu)
+{
+	bool done = false;
+	struct ucall uc;
+	uint64_t val;
+
+	while (!done) {
+		vcpu_run(vcpu);
+
+		switch (get_ucall(vcpu, &uc)) {
+		case UCALL_ABORT:
+			REPORT_GUEST_ASSERT(uc);
+			break;
+		case UCALL_SYNC:
+			/* Make sure the written values are seen by guest */
+			vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(uc.args[2]), &val);
+			TEST_ASSERT_EQ(val, uc.args[3]);
+			break;
+		case UCALL_DONE:
+			done = true;
+			break;
+		default:
+			TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
+		}
+	}
+}
+
+int main(void)
+{
+	struct kvm_vcpu *vcpu;
+	struct kvm_vm *vm;
+	bool aarch64_only;
+	uint64_t val, el0;
+	int ftr_cnt;
+
+	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
+
+	/* Check for AARCH64 only system */
+	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
+	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
+	aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
+
+	ksft_print_header();
+
+	ftr_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
+		  ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
+		  ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
+		  ARRAY_SIZE(ftr_id_aa64mmfr0_el1) + ARRAY_SIZE(ftr_id_aa64mmfr1_el1) +
+		  ARRAY_SIZE(ftr_id_aa64mmfr2_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
+		  ARRAY_SIZE(test_regs);
+
+	ksft_set_plan(ftr_cnt);
+
+	test_user_set_reg(vcpu, aarch64_only);
+	test_guest_reg_read(vcpu);
+
+	kvm_vm_free(vm);
+
+	ksft_finished();
+}
-- 
2.42.0.609.gbb76f46606-goog


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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Cornelia Huck]

On Wed, Oct 11 2023, Oliver Upton <oliver.upton@linux.dev> wrote:

> From: Jing Zhang <jingzhangos@google.com>
>
> Add tests to verify setting ID registers from userspace is handled
> correctly by KVM. Also add a test case to use ioctl
> KVM_ARM_GET_REG_WRITABLE_MASKS to get writable masks.
>
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  tools/testing/selftests/kvm/Makefile          |   1 +
>  .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++++++++++
>  2 files changed, 480 insertions(+)
>  create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c

(...)

> +static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only)
> +{
> +	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
> +	struct reg_mask_range range = {
> +		.addr = (__u64)masks,
> +	};
> +	int ret;
> +
> +	/* KVM should return error when reserved field is not zero */
> +	range.reserved[0] = 1;
> +	ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
> +	TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");

I think the code should first check for
KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES -- newer kselftests are supposed
to be able to run on older kernels, and we should just skip all of this
if the API isn't there.

> +
> +	/* Get writable masks for feature ID registers */
> +	memset(range.reserved, 0, sizeof(range.reserved));
> +	vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);


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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Oliver Upton]

On Mon, Oct 16, 2023 at 05:30:06PM +0200, Cornelia Huck wrote:
> On Wed, Oct 11 2023, Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> > From: Jing Zhang <jingzhangos@google.com>
> >
> > Add tests to verify setting ID registers from userspace is handled
> > correctly by KVM. Also add a test case to use ioctl
> > KVM_ARM_GET_REG_WRITABLE_MASKS to get writable masks.
> >
> > Signed-off-by: Jing Zhang <jingzhangos@google.com>
> > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> > ---
> >  tools/testing/selftests/kvm/Makefile          |   1 +
> >  .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++++++++++
> >  2 files changed, 480 insertions(+)
> >  create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c
> 
> (...)
> 
> > +static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only)
> > +{
> > +	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
> > +	struct reg_mask_range range = {
> > +		.addr = (__u64)masks,
> > +	};
> > +	int ret;
> > +
> > +	/* KVM should return error when reserved field is not zero */
> > +	range.reserved[0] = 1;
> > +	ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
> > +	TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
> 
> I think the code should first check for
> KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES -- newer kselftests are supposed
> to be able to run on older kernels, and we should just skip all of this
> if the API isn't there.

Ah, thanks! I'll apply the following on top:

diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
index 5c0718fd1705..bac05210b539 100644
--- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c
+++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
@@ -452,6 +452,8 @@ int main(void)
 	uint64_t val, el0;
 	int ftr_cnt;
 
+	TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
+
 	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
 
 	/* Check for AARCH64 only system */

-- 
Thanks,
Oliver

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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Cornelia Huck]

On Tue, Oct 17 2023, Oliver Upton <oliver.upton@linux.dev> wrote:

> On Mon, Oct 16, 2023 at 05:30:06PM +0200, Cornelia Huck wrote:
>> On Wed, Oct 11 2023, Oliver Upton <oliver.upton@linux.dev> wrote:
>> 
>> > From: Jing Zhang <jingzhangos@google.com>
>> >
>> > Add tests to verify setting ID registers from userspace is handled
>> > correctly by KVM. Also add a test case to use ioctl
>> > KVM_ARM_GET_REG_WRITABLE_MASKS to get writable masks.
>> >
>> > Signed-off-by: Jing Zhang <jingzhangos@google.com>
>> > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
>> > ---
>> >  tools/testing/selftests/kvm/Makefile          |   1 +
>> >  .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++++++++++
>> >  2 files changed, 480 insertions(+)
>> >  create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c
>> 
>> (...)
>> 
>> > +static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only)
>> > +{
>> > +	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
>> > +	struct reg_mask_range range = {
>> > +		.addr = (__u64)masks,
>> > +	};
>> > +	int ret;
>> > +
>> > +	/* KVM should return error when reserved field is not zero */
>> > +	range.reserved[0] = 1;
>> > +	ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
>> > +	TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
>> 
>> I think the code should first check for
>> KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES -- newer kselftests are supposed
>> to be able to run on older kernels, and we should just skip all of this
>> if the API isn't there.
>
> Ah, thanks! I'll apply the following on top:
>
> diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
> index 5c0718fd1705..bac05210b539 100644
> --- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c
> +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
> @@ -452,6 +452,8 @@ int main(void)
>  	uint64_t val, el0;
>  	int ftr_cnt;
>  
> +	TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
> +
>  	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
>  
>  	/* Check for AARCH64 only system */

Thanks, LGTM.


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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Eric Auger]

Hi,

On 10/11/23 21:57, Oliver Upton wrote:
> From: Jing Zhang <jingzhangos@google.com>

nit: typo in the title
> 
> Add tests to verify setting ID registers from userspace is handled
> correctly by KVM. Also add a test case to use ioctl
> KVM_ARM_GET_REG_WRITABLE_MASKS to get writable masks.
> 
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  tools/testing/selftests/kvm/Makefile          |   1 +
>  .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++++++++++
>  2 files changed, 480 insertions(+)
>  create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c
> 
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index 07b3f4dc1a77..4f4f6ad025f4 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -156,6 +156,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/debug-exceptions
>  TEST_GEN_PROGS_aarch64 += aarch64/hypercalls
>  TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test
>  TEST_GEN_PROGS_aarch64 += aarch64/psci_test
> +TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs
>  TEST_GEN_PROGS_aarch64 += aarch64/smccc_filter
>  TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config
>  TEST_GEN_PROGS_aarch64 += aarch64/vgic_init
> diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
> new file mode 100644
> index 000000000000..5c0718fd1705
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
> @@ -0,0 +1,479 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * set_id_regs - Test for setting ID register from usersapce.
> + *
> + * Copyright (c) 2023 Google LLC.
> + *
> + *
> + * Test that KVM supports setting ID registers from userspace and handles the
> + * feature set correctly.
> + */
> +
> +#include <stdint.h>
> +#include "kvm_util.h"
> +#include "processor.h"
> +#include "test_util.h"
> +#include <linux/bitfield.h>
> +
> +enum ftr_type {
> +	FTR_EXACT,			/* Use a predefined safe value */
practically FTR_EXACT is not used in this patch. Is it worth to keep?
Same question for the associated logic in get_safe/invalid_value
> +	FTR_LOWER_SAFE,			/* Smaller value is safe */
> +	FTR_HIGHER_SAFE,		/* Bigger value is safe */
> +	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */
> +	FTR_END,			/* Mark the last ftr bits */
> +};
> +
> +#define FTR_SIGNED	true	/* Value should be treated as signed */
> +#define FTR_UNSIGNED	false	/* Value should be treated as unsigned */
> +
> +struct reg_ftr_bits {
> +	char *name;
> +	bool sign;
> +	enum ftr_type type;
> +	uint8_t shift;
> +	uint64_t mask;
> +	int64_t safe_val;
> +};
> +
> +struct test_feature_reg {
> +	uint32_t reg;
> +	const struct reg_ftr_bits *ftr_bits;
> +};
> +
> +#define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL)	\
> +	{								\
> +		.name = #NAME,						\
> +		.sign = SIGNED,						\
> +		.type = TYPE,						\
> +		.shift = SHIFT,						\
> +		.mask = MASK,						\
> +		.safe_val = SAFE_VAL,					\
> +	}
> +
> +#define REG_FTR_BITS(type, reg, field, safe_val) \
> +	__REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
> +		       reg##_##field##_MASK, safe_val)
> +
> +#define S_REG_FTR_BITS(type, reg, field, safe_val) \
> +	__REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
> +		       reg##_##field##_MASK, safe_val)
> +
> +#define REG_FTR_END					\
> +	{						\
> +		.type = FTR_END,			\
> +	}
> +
> +static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
> +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
Strictly speaking this is not always safe to have a lower value. For
instance: From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001
is not permitted. But I guess this consistency is to be taken into
account by the user space. But may be wort a comment. Here and below

You may at least clarify what does mean 'safe'
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
> +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
> +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
> +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ASIDBITS, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
> +	REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
> +	REG_FTR_END,
> +};
> +
> +static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
> +	REG_FTR_END,
> +};
> +
> +#define TEST_REG(id, table)			\
> +	{					\
> +		.reg = id,			\
> +		.ftr_bits = &((table)[0]),	\
> +	}
> +
> +static struct test_feature_reg test_regs[] = {
> +	TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
> +	TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
> +	TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
> +	TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
> +	TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
> +	TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
> +	TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
> +	TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
> +	TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
> +	TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
> +};
> +
> +#define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
> +
> +static void guest_code(void)
> +{
> +	GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
> +	GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
> +	GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
> +
> +	GUEST_DONE();
> +}
> +
> +/* Return a safe value to a given ftr_bits an ftr value */
and ftr value
> +uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
> +{
> +	uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
> +
> +	if (ftr_bits->type == FTR_UNSIGNED) {
> +		switch (ftr_bits->type) {
> +		case FTR_EXACT:
> +			ftr = ftr_bits->safe_val;
> +			break;
> +		case FTR_LOWER_SAFE:
> +			if (ftr > 0)
> +				ftr--;
> +			break;
> +		case FTR_HIGHER_SAFE:
> +			if (ftr < ftr_max)
> +				ftr++;
> +			break;
> +		case FTR_HIGHER_OR_ZERO_SAFE:
> +			if (ftr == ftr_max)
> +				ftr = 0;
> +			else if (ftr != 0)
> +				ftr++;
> +			break;
> +		default:
> +			break;
> +		}
> +	} else if (ftr != ftr_max) {
> +		switch (ftr_bits->type) {
> +		case FTR_EXACT:
> +			ftr = ftr_bits->safe_val;
> +			break;
> +		case FTR_LOWER_SAFE:
> +			if (ftr > 0)
> +				ftr--;
> +			break;
> +		case FTR_HIGHER_SAFE:
> +			if (ftr < ftr_max - 1)
> +				ftr++;
> +			break;
> +		case FTR_HIGHER_OR_ZERO_SAFE:
> +			if (ftr != 0 && ftr != ftr_max - 1)
> +				ftr++;
> +			break;
> +		default:
> +			break;
> +		}
> +	}
> +
> +	return ftr;
in some cases we are going to return the same value as ftr and the test
won't do much. Shouldn't we return an error value in that case and skip
the test instead?
> +}
> +
> +/* Return an invalid value to a given ftr_bits an ftr value */
> +uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
> +{
> +	uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
> +
> +	if (ftr_bits->type == FTR_UNSIGNED) {
> +		switch (ftr_bits->type) {
> +		case FTR_EXACT:
> +			ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
> +			break;
> +		case FTR_LOWER_SAFE:
> +			ftr++;
> +			break;
> +		case FTR_HIGHER_SAFE:
> +			ftr--;
> +			break;
> +		case FTR_HIGHER_OR_ZERO_SAFE:
> +			if (ftr == 0)
> +				ftr = ftr_max;
isn't it invalid as ftr_max >= ftr?
> +			else
> +				ftr--;
> +			break;
> +		default:
> +			break;
> +		}
> +	} else if (ftr != ftr_max) {
> +		switch (ftr_bits->type) {
> +		case FTR_EXACT:
> +			ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
> +			break;
> +		case FTR_LOWER_SAFE:
> +			ftr++;
> +			break;
> +		case FTR_HIGHER_SAFE:
> +			ftr--;
> +			break;
> +		case FTR_HIGHER_OR_ZERO_SAFE:
> +			if (ftr == 0)
> +				ftr = ftr_max - 1;
> +			else
> +				ftr--;
> +			break;
> +		default:
> +			break;
> +		}
> +	} else {
> +		ftr = 0;
> +	}
> +
> +	return ftr;
> +}
> +
> +static void test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
> +				 const struct reg_ftr_bits *ftr_bits)
> +{
> +	uint8_t shift = ftr_bits->shift;
> +	uint64_t mask = ftr_bits->mask;
> +	uint64_t val, new_val, ftr;
> +
> +	vcpu_get_reg(vcpu, reg, &val);
> +	ftr = (val & mask) >> shift;
> +
> +	ftr = get_safe_value(ftr_bits, ftr);
> +
> +	ftr <<= shift;
> +	val &= ~mask;
> +	val |= ftr;
> +
> +	vcpu_set_reg(vcpu, reg, val);
> +	vcpu_get_reg(vcpu, reg, &new_val);
> +	TEST_ASSERT_EQ(new_val, val);
> +}
> +
> +static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
> +			      const struct reg_ftr_bits *ftr_bits)
> +{
> +	uint8_t shift = ftr_bits->shift;
> +	uint64_t mask = ftr_bits->mask;
> +	uint64_t val, old_val, ftr;
> +	int r;
> +
> +	vcpu_get_reg(vcpu, reg, &val);
> +	ftr = (val & mask) >> shift;
> +
> +	ftr = get_invalid_value(ftr_bits, ftr);
> +
> +	old_val = val;
> +	ftr <<= shift;
> +	val &= ~mask;
> +	val |= ftr;
> +
> +	r = __vcpu_set_reg(vcpu, reg, val);
> +	TEST_ASSERT(r < 0 && errno == EINVAL,
> +		    "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
> +
> +	vcpu_get_reg(vcpu, reg, &val);
> +	TEST_ASSERT_EQ(val, old_val);
> +}
> +
> +static void test_user_set_reg(struct kvm_vcpu *vcpu, bool aarch64_only)
> +{
> +	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
> +	struct reg_mask_range range = {
> +		.addr = (__u64)masks,
> +	};
> +	int ret;
> +
> +	/* KVM should return error when reserved field is not zero */
> +	range.reserved[0] = 1;
> +	ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
> +	TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
> +
> +	/* Get writable masks for feature ID registers */
> +	memset(range.reserved, 0, sizeof(range.reserved));
> +	vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
> +
> +	for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
> +		const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
> +		uint32_t reg_id = test_regs[i].reg;
> +		uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
> +		int idx;
> +
> +		/* Get the index to masks array for the idreg */
> +		idx = KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(reg_id), sys_reg_Op1(reg_id),
> +						   sys_reg_CRn(reg_id), sys_reg_CRm(reg_id),
> +						   sys_reg_Op2(reg_id));
> +
> +		for (int j = 0;  ftr_bits[j].type != FTR_END; j++) {
> +			/* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
> +			if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
> +				ksft_test_result_skip("%s on AARCH64 only system\n",
> +						      ftr_bits[j].name);
> +				continue;
> +			}
> +
> +			/* Make sure the feature field is writable */
> +			TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
> +
> +			test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
> +			test_reg_set_success(vcpu, reg, &ftr_bits[j]);
> +
> +			ksft_test_result_pass("%s\n", ftr_bits[j].name);
> +		}
> +	}
> +}
> +
> +static void test_guest_reg_read(struct kvm_vcpu *vcpu)
> +{
> +	bool done = false;
> +	struct ucall uc;
> +	uint64_t val;
> +
> +	while (!done) {
> +		vcpu_run(vcpu);
> +
> +		switch (get_ucall(vcpu, &uc)) {
> +		case UCALL_ABORT:
> +			REPORT_GUEST_ASSERT(uc);
> +			break;
> +		case UCALL_SYNC:
> +			/* Make sure the written values are seen by guest */
> +			vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(uc.args[2]), &val);
> +			TEST_ASSERT_EQ(val, uc.args[3]);
> +			break;
> +		case UCALL_DONE:
> +			done = true;
> +			break;
> +		default:
> +			TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
> +		}
> +	}
> +}
> +
> +int main(void)
> +{
> +	struct kvm_vcpu *vcpu;
> +	struct kvm_vm *vm;
> +	bool aarch64_only;
> +	uint64_t val, el0;
> +	int ftr_cnt;
> +
> +	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
> +
> +	/* Check for AARCH64 only system */
> +	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
> +	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
> +	aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
> +
> +	ksft_print_header();
> +
> +	ftr_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
> +		  ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
> +		  ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
> +		  ARRAY_SIZE(ftr_id_aa64mmfr0_el1) + ARRAY_SIZE(ftr_id_aa64mmfr1_el1) +
> +		  ARRAY_SIZE(ftr_id_aa64mmfr2_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
> +		  ARRAY_SIZE(test_regs);
> +
> +	ksft_set_plan(ftr_cnt);
> +
> +	test_user_set_reg(vcpu, aarch64_only);
> +	test_guest_reg_read(vcpu);
> +
> +	kvm_vm_free(vm);
> +
> +	ksft_finished();
> +}

Thanks

Eric


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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Zenghui Yu]

On 2023/10/19 16:38, Eric Auger wrote:

>> +static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
>> +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
 >
> Strictly speaking this is not always safe to have a lower value. For
> instance: From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001
> is not permitted. But I guess this consistency is to be taken into
> account by the user space. But may be wort a comment. Here and below
> 
> You may at least clarify what does mean 'safe'
 >
>> +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),

I've seen the following failure on Cortex A72 where
ID_AA64DFR0_EL1.DebugVer is 6.

# ./aarch64/set_id_regs
TAP version 13
1..79
ok 1 ID_AA64DFR0_EL1_PMUVer
==== Test Assertion Failure ====
   include/kvm_util_base.h:553: !ret
   pid=2288505 tid=2288505 errno=22 - Invalid argument
      1	0x0000000000402787: vcpu_set_reg at kvm_util_base.h:553 
(discriminator 6)
      2	 (inlined by) test_reg_set_success at set_id_regs.c:342 
(discriminator 6)
      3	 (inlined by) test_user_set_reg at set_id_regs.c:413 
(discriminator 6)
      4	0x0000000000401943: main at set_id_regs.c:475
      5	0x0000ffffbdd5d03b: ?? ??:0
      6	0x0000ffffbdd5d113: ?? ??:0
      7	0x0000000000401a2f: _start at ??:?
   KVM_SET_ONE_REG failed, rc: -1 errno: 22 (Invalid argument)

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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Oliver Upton]

Hi Zenghui,

On Fri, Jan 05, 2024 at 05:07:08PM +0800, Zenghui Yu wrote:
> On 2023/10/19 16:38, Eric Auger wrote:
> 
> > > +static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
> > > +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
> >
> > Strictly speaking this is not always safe to have a lower value. For
> > instance: From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001
> > is not permitted. But I guess this consistency is to be taken into
> > account by the user space. But may be wort a comment. Here and below
> > 
> > You may at least clarify what does mean 'safe'
> >
> > > +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),
> 
> I've seen the following failure on Cortex A72 where
> ID_AA64DFR0_EL1.DebugVer is 6.

Ah, yes, the test is wrong. KVM enforces a minimum value of 0x6 on this
field, yet get_safe_value() returns 0x5 for the field.

Jing, do you have time to check this test for similar failures and send
out a fix for Zenghui's observations?

> # ./aarch64/set_id_regs
> TAP version 13
> 1..79
> ok 1 ID_AA64DFR0_EL1_PMUVer
> ==== Test Assertion Failure ====
>   include/kvm_util_base.h:553: !ret
>   pid=2288505 tid=2288505 errno=22 - Invalid argument
>      1	0x0000000000402787: vcpu_set_reg at kvm_util_base.h:553
> (discriminator 6)
>      2	 (inlined by) test_reg_set_success at set_id_regs.c:342
> (discriminator 6)
>      3	 (inlined by) test_user_set_reg at set_id_regs.c:413 (discriminator
> 6)
>      4	0x0000000000401943: main at set_id_regs.c:475
>      5	0x0000ffffbdd5d03b: ?? ??:0
>      6	0x0000ffffbdd5d113: ?? ??:0
>      7	0x0000000000401a2f: _start at ??:?
>   KVM_SET_ONE_REG failed, rc: -1 errno: 22 (Invalid argument)

-- 
Thanks,
Oliver

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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Jing Zhang]

Hi Zenghui,

I don't have a Cortex A72 to fully verify the fix. Could you help
verify the following change?

diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c
b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
index bac05210b539..f17454dc6d9e 100644
--- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c
+++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
@@ -224,13 +224,20 @@ uint64_t get_safe_value(const struct
reg_ftr_bits *ftr_bits, uint64_t ftr)
 {
        uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);

-       if (ftr_bits->type == FTR_UNSIGNED) {
+       if (ftr_bits->sign == FTR_UNSIGNED) {
                switch (ftr_bits->type) {
                case FTR_EXACT:
                        ftr = ftr_bits->safe_val;
                        break;
                case FTR_LOWER_SAFE:
-                       if (ftr > 0)
+                       uint64_t min_safe = 0;
+
+                       if (!strcmp(ftr_bits->name, "ID_AA64DFR0_EL1_DebugVer"))
+                               min_safe = ID_AA64DFR0_EL1_DebugVer_IMP;
+                       else if (!strcmp(ftr_bits->name, "ID_DFR0_EL1_CopDbg"))
+                               min_safe = ID_DFR0_EL1_CopDbg_Armv8;
+
+                       if (ftr > min_safe)
                                ftr--;
                        break;
                case FTR_HIGHER_SAFE:
@@ -252,7 +259,12 @@ uint64_t get_safe_value(const struct reg_ftr_bits
*ftr_bits, uint64_t ftr)
                        ftr = ftr_bits->safe_val;
                        break;
                case FTR_LOWER_SAFE:
-                       if (ftr > 0)
+                       uint64_t min_safe = 0;
+
+                       if (!strcmp(ftr_bits->name, "ID_DFR0_EL1_PerfMon"))
+                               min_safe = ID_DFR0_EL1_PerfMon_PMUv3;
+
+                       if (ftr > min_safe)
                                ftr--;
                        break;
                case FTR_HIGHER_SAFE:
@@ -276,7 +288,7 @@ uint64_t get_invalid_value(const struct
reg_ftr_bits *ftr_bits, uint64_t ftr)
 {
        uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);

-       if (ftr_bits->type == FTR_UNSIGNED) {
+       if (ftr_bits->sign == FTR_UNSIGNED) {
                switch (ftr_bits->type) {
                case FTR_EXACT:
                        ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);

On Mon, Jan 8, 2024 at 2:40 PM Oliver Upton <oliver.upton@linux.dev> wrote:
>
> Hi Zenghui,
>
> On Fri, Jan 05, 2024 at 05:07:08PM +0800, Zenghui Yu wrote:
> > On 2023/10/19 16:38, Eric Auger wrote:
> >
> > > > +static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
> > > > + S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
> > >
> > > Strictly speaking this is not always safe to have a lower value. For
> > > instance: From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001
> > > is not permitted. But I guess this consistency is to be taken into
> > > account by the user space. But may be wort a comment. Here and below
> > >
> > > You may at least clarify what does mean 'safe'
> > >
> > > > + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),
> >
> > I've seen the following failure on Cortex A72 where
> > ID_AA64DFR0_EL1.DebugVer is 6.
>
> Ah, yes, the test is wrong. KVM enforces a minimum value of 0x6 on this
> field, yet get_safe_value() returns 0x5 for the field.
>
> Jing, do you have time to check this test for similar failures and send
> out a fix for Zenghui's observations?
>
> > # ./aarch64/set_id_regs
> > TAP version 13
> > 1..79
> > ok 1 ID_AA64DFR0_EL1_PMUVer
> > ==== Test Assertion Failure ====
> >   include/kvm_util_base.h:553: !ret
> >   pid=2288505 tid=2288505 errno=22 - Invalid argument
> >      1        0x0000000000402787: vcpu_set_reg at kvm_util_base.h:553
> > (discriminator 6)
> >      2         (inlined by) test_reg_set_success at set_id_regs.c:342
> > (discriminator 6)
> >      3         (inlined by) test_user_set_reg at set_id_regs.c:413 (discriminator
> > 6)
> >      4        0x0000000000401943: main at set_id_regs.c:475
> >      5        0x0000ffffbdd5d03b: ?? ??:0
> >      6        0x0000ffffbdd5d113: ?? ??:0
> >      7        0x0000000000401a2f: _start at ??:?
> >   KVM_SET_ONE_REG failed, rc: -1 errno: 22 (Invalid argument)
>
> --
> Thanks,
> Oliver

Thanks,
Jing

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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Zenghui Yu]

On 2024/1/9 09:31, Jing Zhang wrote:
> Hi Zenghui,
> 
> I don't have a Cortex A72 to fully verify the fix. Could you help
> verify the following change?

It works for me (after fixing a compilation error locally ;-) ), thanks!

Zenghui

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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Jing Zhang]

Thanks Zenghui.

On Tue, Jan 9, 2024 at 7:37 AM Zenghui Yu <zenghui.yu@linux.dev> wrote:
>
> On 2024/1/9 09:31, Jing Zhang wrote:
> > Hi Zenghui,
> >
> > I don't have a Cortex A72 to fully verify the fix. Could you help
> > verify the following change?
>
> It works for me (after fixing a compilation error locally ;-) ), thanks!
>
> Zenghui

Jing

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Re: [PATCH v3 5/5] KVM: arm64: selftests: Test for setting ID register from usersapce

[Itaru Kitayama]

On Mon, Jan 08, 2024 at 10:40:11PM +0000, Oliver Upton wrote:
> Hi Zenghui,
> 
> On Fri, Jan 05, 2024 at 05:07:08PM +0800, Zenghui Yu wrote:
> > On 2023/10/19 16:38, Eric Auger wrote:
> > 
> > > > +static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
> > > > +	S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
> > >
> > > Strictly speaking this is not always safe to have a lower value. For
> > > instance: From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001
> > > is not permitted. But I guess this consistency is to be taken into
> > > account by the user space. But may be wort a comment. Here and below
> > > 
> > > You may at least clarify what does mean 'safe'
> > >
> > > > +	REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, 0),
> > 
> > I've seen the following failure on Cortex A72 where
> > ID_AA64DFR0_EL1.DebugVer is 6.
> 
> Ah, yes, the test is wrong. KVM enforces a minimum value of 0x6 on this
> field, yet get_safe_value() returns 0x5 for the field.

This is observed with the RevC AEM FVP as well.

Thanks,
Itaru.

> 
> Jing, do you have time to check this test for similar failures and send
> out a fix for Zenghui's observations?
> 
> > # ./aarch64/set_id_regs
> > TAP version 13
> > 1..79
> > ok 1 ID_AA64DFR0_EL1_PMUVer
> > ==== Test Assertion Failure ====
> >   include/kvm_util_base.h:553: !ret
> >   pid=2288505 tid=2288505 errno=22 - Invalid argument
> >      1	0x0000000000402787: vcpu_set_reg at kvm_util_base.h:553
> > (discriminator 6)
> >      2	 (inlined by) test_reg_set_success at set_id_regs.c:342
> > (discriminator 6)
> >      3	 (inlined by) test_user_set_reg at set_id_regs.c:413 (discriminator
> > 6)
> >      4	0x0000000000401943: main at set_id_regs.c:475
> >      5	0x0000ffffbdd5d03b: ?? ??:0
> >      6	0x0000ffffbdd5d113: ?? ??:0
> >      7	0x0000000000401a2f: _start at ??:?
> >   KVM_SET_ONE_REG failed, rc: -1 errno: 22 (Invalid argument)
> 
> -- 
> Thanks,
> Oliver

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Re: [PATCH v3 0/5] KVM: selftests: Add ID reg test, update headers

[Marc Zyngier]

On Wed, 11 Oct 2023 20:57:35 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> v2: https://lore.kernel.org/kvmarm/20231010011023.2497088-1-oliver.upton@linux.dev/
> 
> v2 -> v3:
>  - Use the kernel's script/data for generating the header instad of a
>    copy (broonie)
> 
> Jing Zhang (2):
>   tools headers arm64: Update sysreg.h with kernel sources
>   KVM: arm64: selftests: Test for setting ID register from usersapce
> 
> Oliver Upton (3):
>   tools: arm64: Add a Makefile for generating sysreg-defs.h
>   perf build: Generate arm64's sysreg-defs.h and add to include path
>   KVM: selftests: Generate sysreg-defs.h and add to include path
> 
>  tools/arch/arm64/include/.gitignore           |   1 +
>  tools/arch/arm64/include/asm/gpr-num.h        |  26 +
>  tools/arch/arm64/include/asm/sysreg.h         | 839 ++++--------------
>  tools/arch/arm64/tools/Makefile               |  38 +
>  tools/perf/Makefile.perf                      |  15 +-
>  tools/perf/util/Build                         |   2 +-
>  tools/testing/selftests/kvm/Makefile          |  24 +-
>  .../selftests/kvm/aarch64/aarch32_id_regs.c   |   4 +-
>  .../selftests/kvm/aarch64/debug-exceptions.c  |  12 +-
>  .../selftests/kvm/aarch64/page_fault_test.c   |   6 +-
>  .../selftests/kvm/aarch64/set_id_regs.c       | 479 ++++++++++
>  .../selftests/kvm/lib/aarch64/processor.c     |   6 +-
>  12 files changed, 785 insertions(+), 667 deletions(-)
>  create mode 100644 tools/arch/arm64/include/.gitignore
>  create mode 100644 tools/arch/arm64/include/asm/gpr-num.h
>  create mode 100644 tools/arch/arm64/tools/Makefile
>  create mode 100644 tools/testing/selftests/kvm/aarch64/set_id_regs.c

With Cornelia's comment addressed,

Acked-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [PATCH v3 0/5] KVM: selftests: Add ID reg test, update headers

[Oliver Upton]

On Wed, 11 Oct 2023 19:57:35 +0000, Oliver Upton wrote:
> v2: https://lore.kernel.org/kvmarm/20231010011023.2497088-1-oliver.upton@linux.dev/
> 
> v2 -> v3:
>  - Use the kernel's script/data for generating the header instad of a
>    copy (broonie)
> 
> Jing Zhang (2):
>   tools headers arm64: Update sysreg.h with kernel sources
>   KVM: arm64: selftests: Test for setting ID register from usersapce
> 
> [...]

Applied to kvmarm/next, thanks!

[1/5] tools: arm64: Add a Makefile for generating sysreg-defs.h
      https://git.kernel.org/kvmarm/kvmarm/c/02e85f74668e
[2/5] perf build: Generate arm64's sysreg-defs.h and add to include path
      https://git.kernel.org/kvmarm/kvmarm/c/e2bdd172e665
[3/5] KVM: selftests: Generate sysreg-defs.h and add to include path
      https://git.kernel.org/kvmarm/kvmarm/c/9697d84cc3b6
[4/5] tools headers arm64: Update sysreg.h with kernel sources
      https://git.kernel.org/kvmarm/kvmarm/c/0359c946b131
[5/5] KVM: arm64: selftests: Test for setting ID register from usersapce
      https://git.kernel.org/kvmarm/kvmarm/c/54a9ea73527d

--
Best,
Oliver

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