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Fri, 14 Feb 2025 11:13:48 +0000 Date: Fri, 14 Feb 2025 11:13:47 +0000 Message-ID: <86o6z4srro.wl-maz@kernel.org> From: Marc Zyngier To: "Sven Peter" Cc: "Alyssa Rosenzweig" , "Hector Martin" , "Bjorn Helgaas" , "Lorenzo Pieralisi" , Krzysztof =?UTF-8?B?V2lsY3p5?= =?UTF-8?B?xYRza2k=?= , "Manivannan Sadhasivam" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Mark Kettenis" , "Stan Skowronek" , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 7/7] PCI: apple: Add T602x PCIe support In-Reply-To: References: <20250211-pcie-t6-v1-0-b60e6d2501bb@rosenzweig.io> <20250211-pcie-t6-v1-7-b60e6d2501bb@rosenzweig.io> <86y0ybsd0d.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sven@svenpeter.dev, alyssa@rosenzweig.io, marcan@marcan.st, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, kettenis@openbsd.org, stan@corellium.com, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250214_031352_024091_E63A296E X-CRM114-Status: GOOD ( 31.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 13 Feb 2025 19:51:31 +0000, "Sven Peter" wrote: > > Hi, > > On Wed, Feb 12, 2025, at 10:55, Marc Zyngier wrote: > > On Tue, 11 Feb 2025 19:54:32 +0000, > > Alyssa Rosenzweig wrote: > >> > >> From: Hector Martin > >> > >> This version of the hardware moved around a bunch of registers, so we > >> drop the old compatible for these and introduce register offset > >> structures to handle the differences. > >> > >> Signed-off-by: Hector Martin > >> Signed-off-by: Alyssa Rosenzweig > >> --- > >> drivers/pci/controller/pcie-apple.c | 125 ++++++++++++++++++++++++++++++------ > >> 1 file changed, 105 insertions(+), 20 deletions(-) > >> > >> diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c > >> index 7f4839fb0a5b15a9ca87337f53c14a1ce08301fc..7c598334427cb56ca066890ac61143ae1d3ed744 100644 > ... > > > >> + else > >> + rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG); > >> + rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK); > >> + > > > > Can you elaborate on this particular change? > > > > I always assumed this was some clock-gating that needed to occur > > *before* the link training was started. This is now taking place after > > training, and the commit message doesn't say anything about it. > > It's been a while but as far as I can tell APPCLK seems to be related > to the IOMMUs attached to this controller. If it's disabled all reads > from the respective IOMMU MMIO either came back as 0xffff.. or SError > (don't remember which one it was) but pcie itself worked just fine > (until any device tried DMA ofc). > > At least on M1 this entire sequence only works because we already > setup PORT_APPCLK_EN inside m1n1. If we didn't do this (like e.g > for the thunderbolt pcie/dart) the DART probe would already fail. OK, so the exact location of this particular write doesn't matter as long as it happens before we start enabling a device on that port. I'm still perplexed by this one though: + if (pcie->hw->port_refclk) + rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK); + else + rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG); which looks like it switches on the reference clock for the port. I have a very vague recollection that it was required early before m1n1/u-boot grew some PCI initialisation (yes, a long while ago). Thanks, M. -- Without deviation from the norm, progress is not possible.