From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD77BC4345F for ; Fri, 12 Apr 2024 10:00:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fpBisbiqM/Yty4Lt/AapddqdQD2YryiQz9D6XIpRaVw=; b=tgTE2R6SYoWOTK YnO9WIxtl2XHKXA0uiYMfhER1QgnbrSdn7aB9gOWij48c+MMpgnXzDCk81SY9LszfapNXV1eB2wJ3 dhG2GrbRgfjqRLmy0XBRyj6ylOeZJLDIG9hZgRWNRDIwgaPxVJjM/JW/iVJ+l1eQ77YUGXH1HkUyK fUkLInW/6NDiK+3OPqB+BiTSG7sI6HB0/cCI7d6LfjsEj9VwqFtWo+xoIA/HQNCEFkvY169MEmgym fo6ZwhhSv2RmYjDoPDC+QR9pB4ctmqXBq+iNU6exikOMHyNmd0Gjx6eeA57jnyTnCYVHXFRGaoshE jd6jf7uzJDgx+MaQzp8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvDhY-0000000GYKm-3Zfg; Fri, 12 Apr 2024 10:00:08 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvDhV-0000000GYK4-30gQ for linux-arm-kernel@lists.infradead.org; Fri, 12 Apr 2024 10:00:07 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 35B67CE386D; Fri, 12 Apr 2024 10:00:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6970FC113CC; Fri, 12 Apr 2024 10:00:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712916002; bh=xNpmaiPO9qZc0AH3VnKJ5wxMnktqXGkEceK9iM9bmyo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=tisJIk+civ6TmIspz41hWpomam1rxjW/1EFHHzpoE2mMaWSFpSfriNrRxWxPnCPT6 xCfMSGF9tWG7xPdGRKldIvg+jOjtSKQXcUVUDjxbtnwXTb6pNwp6EAdsdJ4z5+8Sji KXFgUL8YhC9Ce2AIDItmROsUOCw72HnUA5YBgM9euSpOsSfOkafpUcqo6LY1sovsj6 Mc0wX3CCNoTpGCzQQF6dDe7DCE9ShwRQE7oJ0VvbjpjWLhzW17mosmfaZYUVEQV5rL +8ZWxkh5UqEGI/8oRJC7LCsxyiso1g3C4WeYTOVZbIB2sPu6Z26N9oYeByS4WxTuQN NZgm6SqB2us7g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rvDhQ-003puL-0h; Fri, 12 Apr 2024 11:00:00 +0100 Date: Fri, 12 Apr 2024 10:59:58 +0100 Message-ID: <86o7aesxy9.wl-maz@kernel.org> From: Marc Zyngier To: Yicong Yang Cc: Will Deacon , , , , , , , , , , , , Subject: Re: [PATCH v2 3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime In-Reply-To: References: <20231130074609.58668-1-yangyicong@huawei.com> <20231130074609.58668-4-yangyicong@huawei.com> <20240411142829.GA26681@willie-the-truck> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: yangyicong@huawei.com, will@kernel.org, yangyicong@hisilicon.com, mark.rutland@arm.com, catalin.marinas@arm.com, broonie@kernel.org, james.morse@arm.com, anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, jonathan.cameron@huawei.com, shameerali.kolothum.thodi@huawei.com, prime.zeng@hisilicon.com, fanghao11@huawei.com, linuxarm@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240412_030006_211656_6B71951E X-CRM114-Status: GOOD ( 33.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 12 Apr 2024 10:22:28 +0100, Yicong Yang wrote: > > On 2024/4/11 22:28, Will Deacon wrote: > > On Thu, Nov 30, 2023 at 03:46:09PM +0800, Yicong Yang wrote: > >> From: Yicong Yang > >> > >> On a VHE enabled host, the PMSCR_EL1 will be redirect to PMSCR_EL2 > >> and we're actually enabling E0SPE and E2SPE in the driver. This means > >> the data from EL0&1 translation regime of a VM will not be profiled. > >> So this patch tries to add the support of profiling EL0 and EL1 of > >> a VM. Users can filter data of different exception level by using > >> the perf's exclude_* attributes. The exclude_* decision is referred > >> to Documentation/arch/arm64/perf.rst and the implementation of > >> arm_pmuv3. > >> > >> Signed-off-by: Yicong Yang > >> --- > >> drivers/perf/arm_spe_pmu.c | 37 ++++++++++++++++++++++++++++++------- > >> 1 file changed, 30 insertions(+), 7 deletions(-) > >> > >> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > >> index 09570d4d63cd..a647d625f359 100644 > >> --- a/drivers/perf/arm_spe_pmu.c > >> +++ b/drivers/perf/arm_spe_pmu.c > >> @@ -316,21 +316,44 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) > >> static void arm_spe_pmu_set_pmscr(struct perf_event *event) > >> { > >> struct perf_event_attr *attr = &event->attr; > >> - u64 reg = 0; > >> + u64 pmscr_el1, pmscr_el12; > >> > >> - reg = arm_spe_event_to_pmscr(event); > >> - if (!attr->exclude_user) > >> - reg |= PMSCR_EL1x_E0SPE; > >> + pmscr_el1 = pmscr_el12 = arm_spe_event_to_pmscr(event); > >> + > >> + /* > >> + * Map the exclude_* descision to ELx according to > >> + * Documentation/arch/arm64/perf.rst. > >> + */ > >> + if (is_kernel_in_hyp_mode()) { > >> + if (!attr->exclude_kernel && !attr->exclude_host) > >> + pmscr_el1 |= PMSCR_EL1x_E1SPE; > >> > >> - if (!attr->exclude_kernel) > >> - reg |= PMSCR_EL1x_E1SPE; > >> + if (!attr->exclude_kernel && !attr->exclude_guest) > >> + pmscr_el12 |= PMSCR_EL1x_E1SPE; > >> + > >> + if (!attr->exclude_user && !attr->exclude_host) { > >> + pmscr_el1 |= PMSCR_EL1x_E0SPE; > >> + pmscr_el12 |= PMSCR_EL1x_E0SPE; > >> + } > > > > Hmm, I don't understand this part. Doesn't this mean that setting > > 'exclude_host' to true will also exclude userspace (EL0) profiling for > > the guest? > > > > I may misunderstand 'exclude_host' in the doc. Yes we won't include EL0 here > in the driver but we should handle it on guest enter/exit, which is missed > in this patch. Will see how to handle it properly on guest enter/exit and > respin a v3. Why should you handle this on guest entry/exit? It should be enough to deal with PMCSCR_EL12 at the point where the vcpu is scheduled, and not on the fast path (i.e. it should get hooked into load/put). The PMU does something vaguely similar. Another thing is that it shouldn't get in the way of a future SPE support for the guest itself. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel