From: Marc Zyngier <maz@kernel.org>
To: James Clark <james.clark@arm.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.linux.dev, suzuki.poulose@arm.com,
broonie@kernel.org, Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mike Leach <mike.leach@linaro.org>,
Leo Yan <leo.yan@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Rob Herring <robh@kernel.org>,
Jintack Lim <jintack.lim@linaro.org>,
Fuad Tabba <tabba@google.com>,
Kristina Martsenko <kristina.martsenko@arm.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>,
Joey Gouly <joey.gouly@arm.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/6] arm64: KVM: Add iflag for FEAT_TRF
Date: Mon, 04 Dec 2023 09:48:43 +0000 [thread overview]
Message-ID: <86o7f6b8n8.wl-maz@kernel.org> (raw)
In-Reply-To: <20231019165510.1966367-4-james.clark@arm.com>
On Thu, 19 Oct 2023 17:55:01 +0100,
James Clark <james.clark@arm.com> wrote:
>
> Add an extra iflag to signify if the TRFCR register is accessible.
> Because TRBE requires FEAT_TRF, DEBUG_STATE_SAVE_TRBE still has the same
> behavior even though it's only set when FEAT_TRF is present.
>
> The following holes are left in struct kvm_vcpu_arch, but there aren't
> enough other 8 bit fields to rearrange it to leave any hole smaller than
> 7 bytes:
>
> u8 cflags; /* 2292 1 */
> /* XXX 1 byte hole, try to pack */
> u16 iflags; /* 2294 2 */
> u8 sflags; /* 2296 1 */
> bool pause; /* 2297 1 */
> /* XXX 6 bytes hole, try to pack */
>
> Signed-off-by: James Clark <james.clark@arm.com>
> ---
> arch/arm64/include/asm/kvm_host.h | 4 +++-
> arch/arm64/kvm/debug.c | 22 ++++++++++++++++++----
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 7c82927ddaf2..0f0bf8e641bd 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -535,7 +535,7 @@ struct kvm_vcpu_arch {
> u8 cflags;
>
> /* Input flags to the hypervisor code, potentially cleared after use */
> - u8 iflags;
> + u16 iflags;
>
> /* State flags for kernel bookkeeping, unused by the hypervisor code */
> u8 sflags;
> @@ -741,6 +741,8 @@ struct kvm_vcpu_arch {
> #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
> /* vcpu running in HYP context */
> #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7))
> +/* Save trace filter controls */
> +#define DEBUG_STATE_SAVE_TRFCR __vcpu_single_flag(iflags, BIT(8))
>
> /* SVE enabled for host EL0 */
> #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0))
> diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c
> index 8725291cb00a..20cdd40b3c42 100644
> --- a/arch/arm64/kvm/debug.c
> +++ b/arch/arm64/kvm/debug.c
> @@ -331,14 +331,28 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu)
> !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT)))
> vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE);
>
> - /* Check if we have TRBE implemented and available at the host */
> - if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) &&
> - !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P))
> - vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE);
> + /*
> + * Save TRFCR on nVHE if FEAT_TRF (TraceFilt) exists. This will be
> + * done in cases where use of TRBE doesn't completely disable trace and
> + * handles the exclude_host/exclude_guest rules of the trace session.
This comment provides zero information. What will be done? Under which
conditions? What are the rules?
> + */
> + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) {
> + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRFCR);
> + /*
> + * Check if we have TRBE implemented and available at the host. If it's
> + * in use at the time of guest switch it will need to be disabled and
> + * then restored. The architecture mandates FEAT_TRF with TRBE, so we
> + * only need to check for TRBE after TRF.
> + */
> + if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT) &&
> + !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_P))
> + vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE);
> + }
Multiple questions:
- Why is it safe to trust the local CPU's capability rather than the
consolidated view from the cpufeature infrastructure?
- Why defer the saving of the registers if there are no changes made
to them in the interval?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2023-12-04 9:49 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 16:54 [PATCH v3 0/6] kvm/coresight: Support exclude guest and exclude host James Clark
2023-10-19 16:54 ` [PATCH v3 1/6] arm64/sysreg: Move TRFCR definitions to sysreg James Clark
2023-10-19 16:55 ` [PATCH v3 2/6] arm64: KVM: Move SPE and trace registers to the sysreg array James Clark
2023-12-04 9:29 ` Marc Zyngier
2023-12-04 16:17 ` James Clark
2023-10-19 16:55 ` [PATCH v3 3/6] arm64: KVM: Add iflag for FEAT_TRF James Clark
2023-11-16 19:27 ` Suzuki K Poulose
2023-12-04 9:48 ` Marc Zyngier [this message]
2023-12-05 10:05 ` Suzuki K Poulose
2023-10-19 16:55 ` [PATCH v3 4/6] arm64: KVM: Add interface to set guest value for TRFCR register James Clark
2023-11-16 19:26 ` Suzuki K Poulose
2023-11-22 18:10 ` Suzuki K Poulose
2023-11-24 15:04 ` James Clark
2023-12-04 9:59 ` Marc Zyngier
2023-12-05 9:54 ` James Clark
2023-10-19 16:55 ` [PATCH v3 5/6] arm64: KVM: Write TRFCR value on guest switch with nVHE James Clark
2023-11-16 19:27 ` Suzuki K Poulose
2023-10-19 16:55 ` [PATCH v3 6/6] coresight: Pass guest TRFCR value to KVM James Clark
2023-11-16 19:37 ` Suzuki K Poulose
2023-11-24 11:24 ` James Clark
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