Re: [PATCH 18/43] KVM: arm64: gic-v5: Define remaining IRS MMIO registers

[Marc Zyngier <maz@kernel.org>]

On Mon, 27 Apr 2026 17:12:11 +0100,
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
> 
> Complete the set of defined IRS MMIO registers in the GICv5 header
> file. Up until now, the set of defined IRS MMIO registers has been
> driven by code requirements. However, in order to properly emulate the
> IRS MMIO interface in KVM, the complete set of IRS MMIO registers
> needs to be added.

I really think you need to pick a register update "style". Either you
add all the definitions in one go, or you add them with the patch that
start making use of it.

My preference goes with the former.

> 
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
>  include/linux/irqchip/arm-gic-v5.h | 105 ++++++++++++++++++++++++++---
>  1 file changed, 96 insertions(+), 9 deletions(-)
> 
> diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h
> index 54b573783cd75..9ea3674a6613b 100644
> --- a/include/linux/irqchip/arm-gic-v5.h
> +++ b/include/linux/irqchip/arm-gic-v5.h
> @@ -62,6 +62,14 @@
>  #define GICV5_OUTER_SHARE		0b10
>  #define GICV5_INNER_SHARE		0b11
>  
> +#define GICV5_AIDR_COMPONENT_IRS	0b00
> +#define GICV5_AIDR_COMPONENT_ITS	0b01
> +#define GICV5_AIDR_COMPONENT_IWB	0b10
> +
> +#define GICV5_AIDR_ARCH_MAJ_REV_V5	0
> +#define GICV5_AIDR_ARCH_MIN_REV_V0	0
> +#define GICV5_IIDR_IMPLEMENTER_ARM	0x43b
> +

I'm in two minds about this. We used the same hack (advertising this
as an ARM implementation) for GICv2/v3, but that's really not one.

And in any case, the ARM encoding should not leave in this file -- it
is only used for the KVM implementation, and everything else should be
implementation agnostic (until we need to implement a workaround, of
course...).

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.