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Mon, 23 Feb 2026 09:48:25 +0000 Date: Mon, 23 Feb 2026 09:48:24 +0000 Message-ID: <86pl5vaizb.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Will Deacon , Catalin Marinas , Mark Rutland , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH 1/9] arm64: Add logic to fully remove features from sanitised id registers In-Reply-To: References: <20260219195533.2455736-1-maz@kernel.org> <20260219195533.2455736-2-maz@kernel.org> <86v7frafpx.wl-maz@kernel.org> <86tsvba2nc.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Fuad, On Fri, 20 Feb 2026 15:36:37 +0000, Fuad Tabba wrote: > > > I think we must prevent this downgrade the same way, meaning that > > ALL_HIDDEN and FTR_HIGHER are mutually exclusive. > > > > How about that: > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index d58931e63a0b6..2cae00b4b0c5f 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -1067,7 +1067,14 @@ static void init_cpu_ftr_reg(u32 sys_reg, u64 new) > > user_mask |= ftr_mask; > > break; > > case FTR_ALL_HIDDEN: > > - val = arm64_ftr_set_value(ftrp, val, ftrp->safe_val); > > + /* > > + * ALL_HIDDEN and HIGHER_SAFE are incompatible. > > + * Only hide from userspace, and log the oddity. > > + */ > > + if (WARN_ON(ftrp->type == FTR_HIGHER_SAFE)) > > + val = arm64_ftr_set_value(ftrp, val, ftr_new); > > + else > > + val = arm64_ftr_set_value(ftrp, val, ftrp->safe_val); > > reg->user_val = arm64_ftr_set_value(ftrp, > > reg->user_val, > > ftrp->safe_val); > > > > Yes, I think WARN_ON() here is the right call. > > That said, I still think you should explicitly short-circuit > update_cpu_ftr_reg() for FTR_ALL_HIDDEN features, in addition to the > WARN_ON(). Relying on arm64_ftr_safe_value() to naturally preserve the > safe_val during secondary CPU boot seems mathematically fragile. > > Take MTE_frac as an example. It uses S_ARM64_FTR_BITS and > FTR_LOWER_SAFE with a safe_val of 0. If it were marked FTR_ALL_HIDDEN, > init_cpu_ftr_reg() would prime sys_val with 0. But if a secondary CPU > boots and reports -1 (NI), arm64_ftr_safe_value() will execute min(-1, > 0) and return -1. update_cpu_ftr_reg() will then overwrite the primed > safe_val (0) with -1. The "hidden" state established by the boot CPU > is gone, and the feature's hardware state is now exposed globally. > > Note that MTE is currently ALL_HIDDEN when configured out, so it's not > totally inconceivable that someone decides to make MTE_frac ALL_HIDDEN > as well. Explicitly short-circuiting for FTR_ALL_HIDDEN features in > update_cpu_ftr_reg() seems to be the safer bet here. Right, the signed feature is a pretty compelling argument. And we should do the same thing for overrides, probably as a preliminary patch. Thanks, M. -- Without deviation from the norm, progress is not possible.