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Fri, 20 Oct 2023 14:41:35 +0100 Date: Fri, 20 Oct 2023 14:41:29 +0100 Message-ID: <86pm19o1h2.wl-maz@kernel.org> From: Marc Zyngier To: Ryan Roberts Cc: Catalin Marinas , Will Deacon , Oliver Upton , Suzuki K Poulose , James Morse , Zenghui Yu , Ard Biesheuvel , Anshuman Khandual , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v4 01/12] arm64/mm: Update non-range tlb invalidation routines for FEAT_LPA2 In-Reply-To: <59a62837-1adf-43a5-8716-8068ddbdb7cf@arm.com> References: <20231009185008.3803879-1-ryan.roberts@arm.com> <20231009185008.3803879-2-ryan.roberts@arm.com> <87zg0f59ae.wl-maz@kernel.org> <86edhpn2gd.wl-maz@kernel.org> <8a098442-4de8-42f1-9308-848a1d54f21a@arm.com> <87v8b15twh.wl-maz@kernel.org> <59a62837-1adf-43a5-8716-8068ddbdb7cf@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ryan.roberts@arm.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, suzuki.poulose@arm.com, james.morse@arm.com, yuzenghui@huawei.com, ardb@kernel.org, anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231020_064138_726227_11E41627 X-CRM114-Status: GOOD ( 32.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 20 Oct 2023 14:21:39 +0100, Ryan Roberts wrote: > > On 20/10/2023 14:02, Marc Zyngier wrote: > > On Fri, 20 Oct 2023 13:39:47 +0100, > > Ryan Roberts wrote: > >> > >> On 20/10/2023 09:05, Marc Zyngier wrote: > >>> Maybe. There is something to be said about making the range rework > >>> (decreasing scale) an independent patch, as it is a significant change > >>> on its own. But maybe the rest of the plumbing can be grouped > >>> together. > >> > >> But that's effectively the split I have now, isn't it? The first patch > >> introduces TLBI_TTL_UNKNOWN to enable use of 0 as a ttl hint. Then the second > >> patch reworks the range stuff. I don't quite follow what you are suggesting. > > > > Not quite. > > > > What I'm proposing is that you pull the scale changes in their own > > patch, and preferably without any change to the external API (i.e. no > > change to the signature of the helper). They any extra change, such as > > the TTL rework can go separately. > > > > So while this is similar to your existing split, I'd like to see it > > without any churn around the calling convention. Which means turning > > the ordering around, and making use of a static key in the various > > helpers that need to know about LPA2. > > I don't think we can embed the static key usage directly inside > __flush_tlb_range_op() (if that's what you were suggesting), because this macro > is used by both the kernel (for its stage 1) and the hypervisor (for stage 2). > And the kernel doesn't support LPA2 (until Ard's work is merged). So I think > this needs to be an argument to the macro. I can see two outcomes here: - either you create separate helpers that abstract the LPA2-ness for KVM and stick to non-LPA2 for the kernel (until Ard's series makes it in) - or you leave the whole thing disabled until we have full LPA2 support. Eventually, you replace the whole extra parameter with a static key, and nobody sees any churn. > Or are you asking that I make the scale change universally, even if LPA2 is not > in use? I could do that as its own change change (which I could benchmark), then > add the rest in a separate change. But my thinking was that we would not want to > change the algorithm for !LAP2 since it is not as effcient (due to the LPA2 64K > alignment requirement). I'm all for simplicity. If having an extra 15 potential TLBIs is acceptable from a performance perspective, I won't complain. But I can imagine that NV would be suffering from that (TLBIs on S2 have to trap). M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel